// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
// Netlist written on Tue Feb 09 19:17:21 2021
//
// Verilog Description of module OLED12832
//

module OLED12832 (clk, rst_n, hour_h, hour_l, min_h, min_l, temp_h, 
            temp_l, temp_p, oled_csn, oled_rst, oled_dcn, oled_clk, 
            oled_dat) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(18[8:17])
    input clk;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(20[11:14])
    input rst_n;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(21[11:16])
    input [3:0]hour_h;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(23[15:21])
    input [3:0]hour_l;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(24[15:21])
    input [3:0]min_h;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(25[15:20])
    input [3:0]min_l;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(26[15:20])
    input [3:0]temp_h;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(28[15:21])
    input [3:0]temp_l;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(29[15:21])
    input [3:0]temp_p;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(30[15:21])
    output oled_csn;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(32[15:23])
    output oled_rst;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(33[15:23])
    output oled_dcn;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(34[15:23])
    output oled_clk;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(35[15:23])
    output oled_dat;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(36[15:23])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(20[11:14])
    
    wire GND_net, VCC_net, rst_n_c, hour_h_c_3, hour_h_c_2, hour_h_c_1, 
        hour_h_c_0, hour_l_c_3, hour_l_c_2, hour_l_c_1, hour_l_c_0, 
        min_h_c_3, min_h_c_2, min_h_c_1, min_h_c_0, min_l_c_3, min_l_c_2, 
        min_l_c_1, min_l_c_0, temp_h_c_3, temp_h_c_2, temp_h_c_1, 
        temp_h_c_0, temp_l_c_3, temp_l_c_2, temp_l_c_1, temp_l_c_0, 
        temp_p_c_3, temp_p_c_2, temp_p_c_1, temp_p_c_0, oled_csn_c, 
        oled_rst_c, oled_dcn_c, oled_clk_c, oled_dat_c;
    wire [7:0]y_p;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(46[12:15])
    wire [7:0]x_ph;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(46[17:21])
    
    wire n14097;
    wire [7:0]x_pl;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(46[23:27])
    wire [167:0]char;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(47[19:23])
    wire [7:0]num;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(48[12:15])
    wire [7:0]char_reg;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(48[17:25])
    wire [4:0]cnt_main;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[12:20])
    wire [4:0]cnt_init;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[22:30])
    wire [4:0]cnt_scan;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[32:40])
    wire [4:0]cnt_write;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[42:51])
    wire [15:0]num_delay;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[13:22])
    wire [15:0]cnt_delay;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[24:33])
    wire [15:0]cnt;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[35:38])
    wire [5:0]state;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    wire [5:0]state_back;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[20:30])
    
    wire n7, n8, n10;
    wire [4:0]cnt_main_4__N_298;
    
    wire n30, clk_c_enable_84, n14025;
    wire [7:0]x_ph_7__N_326;
    
    wire clk_c_enable_38, n15845, n28, n10_adj_1, n11112, n25, n11097;
    wire [167:0]char_167__N_358;
    
    wire n245, n246, n247, n248, oled_dcn_N_650, n281, n282, n283, 
        n284, n285, n286, n287, n288, n289, n290, n291, n292, 
        n293, n294, n295, n296, n307, n308, n309, n310, n311, 
        n312, n313, n314, n315, n316, n317, n318, n319, n320, 
        n321, n322, n23, n17220, n16098;
    wire [15:0]num_delay_15__N_542;
    wire [5:0]state_5__N_596;
    
    wire n17767;
    wire [5:0]state_back_5__N_620;
    
    wire clk_c_enable_36, n18425, n17670, n445, n14000, n456, n457, 
        n458;
    wire [4:0]cnt_scan_4__N_308;
    
    wire n647, n812, n813, n814, n815, n816, n817, n818, n1190, 
        n1191, n1192, n1193, n1194, n1195, n1196, n1568, n1569, 
        n1570, n1571, n1572, n1573, n1574, n1946, n1947, n1948, 
        n1949, n1950, n1951, n1952, n2324, n2325, n2326, n2327, 
        n2328, n2329, n2330, n10105, n17766, n16826, n17378, n17765, 
        n42, n2384, n2385, n2386, n2387, oled_csn_N_634, oled_clk_N_670, 
        oled_dat_N_672, n2405, n2408, n2409, n2410, n2411, n2412, 
        n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, 
        n2421, n2422, n2423, n11401, n17962;
    wire [7:0]x_ph_7__N_11;
    
    wire n17961, n17960, n18347;
    wire [7:0]char_reg_7__N_203;
    wire [15:0]num_delay_15__N_231;
    
    wire n17759, n15844;
    wire [5:0]state_back_5__N_285;
    
    wire n15829, n15843, n15834, n41, n5222, n4181, n15842, n9, 
        n15841, n15856, n17208, n15833, n15840, n15855, n63, n64, 
        n61, n16110, n15832, n15839, n18138, n10247, n18017, n22, 
        n57, clk_c_enable_55, n18346, n18371, clk_c_enable_72, n18417, 
        n18370, n15831, n15854, n8_adj_2, n12265, n64_adj_3, n17466, 
        n15, n12270, n47, n5296, n5285, n17255, n11842, n17764, 
        n18339, n17762, n17353, n38, n15830, n14161, n126, n17218, 
        n20, n9_adj_4, n19, n18416, n11847, n6, n15838, n17458, 
        n15853, n17217, n15_adj_5, n3784, n3783, n3782, n3781, 
        n18345, n3778, n3777, n14151, n17457, n44, n15837, n63_adj_6, 
        n64_adj_7, n61_adj_8, n15836, n18, n17272, n11, n17922, 
        n4, n17456, n4_adj_9, n17921, n39, n57_adj_10, n14147, 
        n11507, n63_adj_11, n64_adj_12, n18296, n18726, clk_c_enable_31, 
        n18295, n18415, n55, n19019, n19_adj_13, n18724, n39_adj_14, 
        n45, n15852, n18294, n57_adj_15, n43, n18723, n18293, 
        n18369, n17267, n64_adj_16, n17454, n18292, n18722, n18291, 
        n18290, n18414, n18413, n14137, n24, n18721, n18412, n16, 
        n18281, n18280, n18279, n16_adj_17, n16_adj_18, n15892, 
        n17444, n17788, n18411, n18410, n18253, n18252, n15851, 
        n19020, n16_adj_19, n24_adj_20, n16_adj_21, n11483, n16_adj_22, 
        n18230, n18229, n16_adj_23, n18228, n16_adj_24, n16_adj_25, 
        n18221, n18220, n16_adj_26, n71, n18916, n18915, n18914, 
        n18913, n18912, n18911, n9_adj_27, n17787, n18204, n38_adj_28, 
        n18910, n18420, n24_adj_29, n6_adj_30, n18177, n18406, n18405, 
        n31, n18404, n18403, n35, n24_adj_31, n17313, n24_adj_32, 
        n6_adj_33, n17786, n18402, n18367, n15910, n18401, n18400, 
        n17438, n45_adj_34, n51, clk_c_enable_82, n4_adj_35, n34, 
        n8013, n8014, n8015, n8016, n18366, n17872, n16_adj_36, 
        n18176, n16_adj_37, clk_c_enable_76, n18340, n18365, n16_adj_38, 
        n18173, n18172, n24_adj_39, n16_adj_40, n16_adj_41, n19_adj_42, 
        n18163, n16_adj_43, n18158, n18419, n18156, n16_adj_44, 
        n18155, n18154, n24_adj_45, n6_adj_46, n27, n12, n11894, 
        n24_adj_47, n6_adj_48, n1866, n12_adj_49, n18145, n17366, 
        n17216, n24_adj_50, n6_adj_51, n12_adj_52, n92, n4_adj_53, 
        n24_adj_54, n6_adj_55, n12_adj_56, n6_adj_57, n15835, n12_adj_58, 
        n18137, clk_c_enable_73, n24_adj_59, n6_adj_60, n18399, n14127, 
        n17785, n11909, n18398, n11892, n18397, n18396, n18128, 
        n67, n18127, n18126, n18125, n18124, n15850, n17435, n15863, 
        n15849, n2130, n2131, n2132, n17486, n18395, n18363, n18394, 
        n18115, n18114, n17783, n14, n18393, n18392, n24_adj_61, 
        n6_adj_62, n17782, n12_adj_63, n18113, n18112, n11846, n24_adj_64, 
        n6_adj_65, n12_adj_66, n18111, n18110, n24_adj_67, n6_adj_68, 
        n12_adj_69, n40, clk_c_enable_5, n11_adj_70, n17270, n16_adj_71, 
        n19_adj_72, n18391, n18390, n18362, n17354, n7267, n18361, 
        n10248, n18389, n15848, n28_adj_73, n18360, n9238, clk_c_enable_19, 
        n18004, n15847, clk_c_enable_83, n18387, n17995, n18386, 
        n18358, n18385, n64_adj_74, n17546, n17209, n11888, n11887, 
        n17213, n18080, n18034, n18022, n17197, n17266, n18079, 
        n15846, n16_adj_75, n11759, n18078, n11870, n16300, n13963, 
        n18077, n17281, n17781, n17780, n31_adj_76, n81, n18073, 
        n9122, n11884, n18072, n16_adj_77, n18071, n18070, n19_adj_78, 
        n17779, n16_adj_79, n16_adj_80, n16_adj_81, n42_adj_82, n41_adj_83, 
        n34_adj_84, n18418, n44_adj_85, n17778, n50, n17207, n19018, 
        clk_c_enable_79, n14143, n18383, n11202, n18356, n18382, 
        n33, n11_adj_86, n16021, n8230, n11418, n17256, n13907, 
        n11852, n4_adj_87, n18381, n18355, clk_c_enable_75, n17761, 
        n17273, n18036, n17528, n6_adj_88, n18035, n18380, n18354, 
        n18353, n4_adj_89, n18379, n18352, n39_adj_90, n18015, n17422, 
        n4_adj_91, n17307, n37, n33_adj_92, n18009, n18378, n18008, 
        n18007, n18006, n17760, n17769, n18005, n18377, clk_c_enable_37, 
        n16974, n18037, n18376, n17494, clk_c_enable_59, n17491, 
        n17275, n18350, n17259, n18001, n17304, n18000, n17999, 
        n18375, n17997, n17996, n17200, n18374, n17490, n17489, 
        n17488, n17487, n17992, n17991, n18373, n18349, n18342, 
        n18348, n17202, n4_adj_93, n4_adj_94, n18427, n8_adj_95, 
        n7_adj_96, n17768, n18426;
    
    VHI i10012 (.Z(VCC_net));
    LUT4 i1_4_lut_4_lut (.A(state[0]), .B(n19_adj_42), .C(n16_adj_40), 
         .D(num_delay[12]), .Z(num_delay_15__N_231[12])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut.init = 16'hdc50;
    FD1S3AX num_delay_i4 (.D(num_delay_15__N_231[4]), .CK(clk_c), .Q(num_delay[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i4.GSR = "ENABLED";
    FD1S3AX num_delay_i3 (.D(num_delay_15__N_231[3]), .CK(clk_c), .Q(num_delay[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i3.GSR = "ENABLED";
    FD1S3AY num_delay_i2 (.D(num_delay_15__N_231[2]), .CK(clk_c), .Q(num_delay[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i2.GSR = "ENABLED";
    FD1S3AX num_delay_i1 (.D(num_delay_15__N_231[1]), .CK(clk_c), .Q(num_delay[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i1.GSR = "ENABLED";
    FD1S3AX state_back_i5 (.D(state_back_5__N_285[5]), .CK(clk_c), .Q(state_back[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i5.GSR = "ENABLED";
    FD1S3AX state_back_i4 (.D(state_back_5__N_285[4]), .CK(clk_c), .Q(state_back[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i4.GSR = "ENABLED";
    FD1S3AX state_back_i3 (.D(state_back_5__N_285[3]), .CK(clk_c), .Q(state_back[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i3.GSR = "ENABLED";
    FD1S3AX state_back_i2 (.D(state_back_5__N_285[2]), .CK(clk_c), .Q(state_back[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i2.GSR = "ENABLED";
    FD1S3AX state_back_i1 (.D(state_back_5__N_285[1]), .CK(clk_c), .Q(state_back[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i1.GSR = "ENABLED";
    PFUMX i9485 (.BLUT(n18079), .ALUT(n18077), .C0(n18397), .Z(n18080));
    FD1P3AX state_i0_i1 (.D(n16098), .SP(clk_c_enable_84), .CK(clk_c), 
            .Q(state[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i1.GSR = "ENABLED";
    FD1S3AX char_reg_i7 (.D(char_reg_7__N_203[7]), .CK(clk_c), .Q(char_reg[7]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i7.GSR = "ENABLED";
    FD1S3AX char_reg_i6 (.D(char_reg_7__N_203[6]), .CK(clk_c), .Q(char_reg[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i6.GSR = "ENABLED";
    FD1S3AX char_reg_i5 (.D(char_reg_7__N_203[5]), .CK(clk_c), .Q(char_reg[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i5.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i13 (.D(n2410), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[13]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i13.GSR = "ENABLED";
    CCU2D add_107_15 (.A0(cnt_delay[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n15843), .COUT(n15844), .S0(n2410), .S1(n2409));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_15.INIT0 = 16'h5aaa;
    defparam add_107_15.INIT1 = 16'h5aaa;
    defparam add_107_15.INJECT1_0 = "NO";
    defparam add_107_15.INJECT1_1 = "NO";
    FD1S3AX char_reg_i4 (.D(char_reg_7__N_203[4]), .CK(clk_c), .Q(char_reg[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i4.GSR = "ENABLED";
    FD1S3AX char_reg_i3 (.D(char_reg_7__N_203[3]), .CK(clk_c), .Q(char_reg[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i3.GSR = "ENABLED";
    FD1S3AX char_reg_i2 (.D(char_reg_7__N_203[2]), .CK(clk_c), .Q(char_reg[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i2.GSR = "ENABLED";
    FD1S3AX char_reg_i1 (.D(char_reg_7__N_203[1]), .CK(clk_c), .Q(char_reg[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i1.GSR = "ENABLED";
    FD1S3AX x_ph_i4 (.D(x_ph_7__N_11[4]), .CK(clk_c), .Q(x_ph[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam x_ph_i4.GSR = "ENABLED";
    FD1S3AX x_ph_i2 (.D(x_ph_7__N_11[2]), .CK(clk_c), .Q(x_ph[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam x_ph_i2.GSR = "ENABLED";
    FD1S3AX x_ph_i1 (.D(x_ph_7__N_11[1]), .CK(clk_c), .Q(x_ph[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam x_ph_i1.GSR = "ENABLED";
    FD1P3AX y_p_i0_i0 (.D(n13963), .SP(clk_c_enable_75), .CK(clk_c), .Q(y_p[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam y_p_i0_i0.GSR = "ENABLED";
    FD1S3AX x_ph_i0 (.D(x_ph_7__N_11[0]), .CK(clk_c), .Q(x_ph[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam x_ph_i0.GSR = "ENABLED";
    FD1S3AX char_reg_i0 (.D(char_reg_7__N_203[0]), .CK(clk_c), .Q(char_reg[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_reg_i0.GSR = "ENABLED";
    FD1P3AY state_i0_i0 (.D(n42_adj_82), .SP(clk_c_enable_84), .CK(clk_c), 
            .Q(state[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i0.GSR = "ENABLED";
    FD1P3AY oled_csn_309 (.D(n16974), .SP(clk_c_enable_5), .CK(clk_c), 
            .Q(oled_csn_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam oled_csn_309.GSR = "ENABLED";
    FD1S3AY state_back_i0 (.D(state_back_5__N_285[0]), .CK(clk_c), .Q(state_back[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_back_i0.GSR = "ENABLED";
    FD1S3AY num_delay_i0 (.D(num_delay_15__N_231[0]), .CK(clk_c), .Q(num_delay[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i0.GSR = "ENABLED";
    FD1P3IX cnt_init_i0_i1 (.D(n248), .SP(clk_c_enable_55), .CD(n12265), 
            .CK(clk_c), .Q(cnt_init[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_init_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_scan_i0_i4 (.D(n17200), .SP(clk_c_enable_19), .CK(clk_c), 
            .Q(cnt_scan[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_scan_i0_i4.GSR = "ENABLED";
    FD1P3IX cnt_i0_i8 (.D(n314), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[8]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i8.GSR = "ENABLED";
    FD1P3IX cnt_i0_i9 (.D(n313), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[9]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i9.GSR = "ENABLED";
    FD1P3IX cnt_scan_i0_i3 (.D(cnt_scan_4__N_308[3]), .SP(clk_c_enable_19), 
            .CD(n11909), .CK(clk_c), .Q(cnt_scan[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_scan_i0_i3.GSR = "ENABLED";
    LUT4 i1_3_lut_4_lut (.A(cnt_init[0]), .B(n18382), .C(n92), .D(oled_dcn_N_650), 
         .Z(n17354)) /* synthesis lut_function=(!(A (C)+!A (B (C)+!B !((D)+!C)))) */ ;
    defparam i1_3_lut_4_lut.init = 16'h1f0f;
    FD1P3IX cnt_scan_i0_i2 (.D(cnt_scan_4__N_308[2]), .SP(clk_c_enable_19), 
            .CD(n11909), .CK(clk_c), .Q(cnt_scan[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_scan_i0_i2.GSR = "ENABLED";
    ROM128X1A mux_505_Mux_37 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n813)) /* synthesis initstate=0x00A5E93E05A7FDF7016980700000FD69 */ ;
    defparam mux_505_Mux_37.initval = 128'h00A5E93E05A7FDF7016980700000FD69;
    ROM128X1A mux_505_Mux_30 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1190)) /* synthesis initstate=0x04A8927EACAA96B54BEF426800007BEF */ ;
    defparam mux_505_Mux_30.initval = 128'h04A8927EACAA96B54BEF426800007BEF;
    ROM128X1A mux_505_Mux_22 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1568)) /* synthesis initstate=0x0478923EBE7A96BD836F405000007B6F */ ;
    defparam mux_505_Mux_22.initval = 128'h0478923EBE7A96BD836F405000007B6F;
    ROM128X1A mux_505_Mux_14 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1946)) /* synthesis initstate=0x04989E3EACA892A5117F11080000597F */ ;
    defparam mux_505_Mux_14.initval = 128'h04989E3EACA892A5117F11080000597F;
    ROM128X1A mux_505_Mux_6 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2324)) /* synthesis initstate=0x07226192950679A20004004000004404 */ ;
    defparam mux_505_Mux_6.initval = 128'h07226192950679A20004004000004404;
    ROM128X1A mux_505_Mux_39 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n812)) /* synthesis initstate=0x050D6D04950D7976000400200000EC04 */ ;
    defparam mux_505_Mux_39.initval = 128'h050D6D04950D7976000400200000EC04;
    ROM128X1A mux_505_Mux_8 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n1952)) /* synthesis initstate=0x000004402C1F86E593FD012C0000DBFD */ ;
    defparam mux_505_Mux_8.initval = 128'h000004402C1F86E593FD012C0000DBFD;
    ROM128X1A mux_505_Mux_9 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n1951)) /* synthesis initstate=0x0000000070002C120018007C00002418 */ ;
    defparam mux_505_Mux_9.initval = 128'h0000000070002C120018007C00002418;
    ROM128X1A mux_505_Mux_10 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1950)) /* synthesis initstate=0x040DEDAF2500040060B1820C000000B1 */ ;
    defparam mux_505_Mux_10.initval = 128'h040DEDAF2500040060B1820C000000B1;
    ROM128X1A mux_505_Mux_11 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1949)) /* synthesis initstate=0x05020410320D05EC835C2E180000CB5C */ ;
    defparam mux_505_Mux_11.initval = 128'h05020410320D05EC835C2E180000CB5C;
    ROM128X1A mux_505_Mux_12 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1948)) /* synthesis initstate=0x000A0422210044036010022800000410 */ ;
    defparam mux_505_Mux_12.initval = 128'h000A0422210044036010022800000410;
    ROM128X1A mux_505_Mux_13 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1947)) /* synthesis initstate=0x0361048030460C100210105800002210 */ ;
    defparam mux_505_Mux_13.initval = 128'h0361048030460C100210105800002210;
    FD1P3IX cnt_main_i0_i1 (.D(n10), .SP(clk_c_enable_76), .CD(n11847), 
            .CK(clk_c), .Q(cnt_main[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_main_i0_i1.GSR = "ENABLED";
    ROM128X1A mux_505_Mux_16 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1574)) /* synthesis initstate=0x000012407C1F86FF83EF00D20000FFEF */ ;
    defparam mux_505_Mux_16.initval = 128'h000012407C1F86FF83EF00D20000FFEF;
    ROM128X1A mux_505_Mux_17 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1573)) /* synthesis initstate=0x00001001001002085C120F9200000012 */ ;
    defparam mux_505_Mux_17.initval = 128'h00001001001002085C120F9200000012;
    ROM128X1A mux_505_Mux_18 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1572)) /* synthesis initstate=0x041FD7BE10102A082C2A0C5A0000002A */ ;
    defparam mux_505_Mux_18.initval = 128'h041FD7BE10102A082C2A0C5A0000002A;
    ROM128X1A mux_505_Mux_19 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1571)) /* synthesis initstate=0x00003A40059D63E503C3AC320000CBC3 */ ;
    defparam mux_505_Mux_19.initval = 128'h00003A40059D63E503C3AC320000CBC3;
    ROM128X1A mux_505_Mux_20 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1570)) /* synthesis initstate=0x0588322212960A0BAC160C5800000416 */ ;
    defparam mux_505_Mux_20.initval = 128'h0588322212960A0BAC160C5800000416;
    ROM128X1A mux_505_Mux_21 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1569)) /* synthesis initstate=0x02831A80029002085C025F1200000002 */ ;
    defparam mux_505_Mux_21.initval = 128'h02831A80029002085C025F1200000002;
    FD1P3IX cnt_main_i0_i3 (.D(n8), .SP(clk_c_enable_76), .CD(n11847), 
            .CK(clk_c), .Q(cnt_main[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_main_i0_i3.GSR = "ENABLED";
    PFUMX i9481 (.BLUT(n18072), .ALUT(n18070), .C0(state[3]), .Z(n18073));
    LUT4 i3550_2_lut_3_lut (.A(n18371), .B(n18370), .C(n18354), .Z(n11892)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i3550_2_lut_3_lut.init = 16'h2020;
    FD1P3AX num_1426__i4 (.D(n51), .SP(clk_c_enable_72), .CK(clk_c), .Q(num[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i4.GSR = "ENABLED";
    LUT4 i97_4_lut_4_lut_4_lut (.A(cnt_scan[0]), .B(x_ph[4]), .C(cnt_scan[2]), 
         .D(n814), .Z(n45)) /* synthesis lut_function=(A (C (D))+!A !((C)+!B)) */ ;
    defparam i97_4_lut_4_lut_4_lut.init = 16'ha404;
    LUT4 i1_4_lut_4_lut_adj_1 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_25), 
         .D(num_delay[7]), .Z(num_delay_15__N_231[7])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_1.init = 16'hdc50;
    FD1P3IX cnt_scan_i0_i1 (.D(cnt_scan_4__N_308[1]), .SP(clk_c_enable_19), 
            .CD(n11909), .CK(clk_c), .Q(cnt_scan[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_scan_i0_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut_4_lut (.A(n18386), .B(cnt_main[0]), .C(cnt_main[1]), 
         .D(n9_adj_27), .Z(n4_adj_91)) /* synthesis lut_function=(A (D)+!A (B+(C+(D)))) */ ;
    defparam i1_2_lut_4_lut_4_lut.init = 16'hff54;
    FD1P3IX cnt_init_i0_i2 (.D(n247), .SP(clk_c_enable_55), .CD(n12265), 
            .CK(clk_c), .Q(cnt_init[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_init_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i4 (.D(n2419), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i4.GSR = "ENABLED";
    LUT4 i5570_4_lut_4_lut (.A(cnt_main[0]), .B(cnt_main[1]), .C(n18410), 
         .D(n18387), .Z(n13907)) /* synthesis lut_function=(A ((D)+!B)+!A (B+(C))) */ ;
    defparam i5570_4_lut_4_lut.init = 16'hfe76;
    CCU2D add_107_13 (.A0(cnt_delay[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n15842), .COUT(n15843), .S0(n2412), .S1(n2411));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_13.INIT0 = 16'h5aaa;
    defparam add_107_13.INIT1 = 16'h5aaa;
    defparam add_107_13.INJECT1_0 = "NO";
    defparam add_107_13.INJECT1_1 = "NO";
    LUT4 n649_bdd_4_lut_4_lut (.A(n18363), .B(n2132), .C(num[4]), .D(n2131), 
         .Z(n18220)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !((C+(D))+!B)) */ ;
    defparam n649_bdd_4_lut_4_lut.init = 16'ha204;
    FD1P3IX cnt_delay_i0_i5 (.D(n2418), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i5.GSR = "ENABLED";
    ROM128X1A mux_505_Mux_1 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2329)) /* synthesis initstate=0x0000005007E7E1858385803000001B85 */ ;
    defparam mux_505_Mux_1.initval = 128'h0000005007E7E1858385803000001B85;
    ROM128X1A mux_505_Mux_2 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2328)) /* synthesis initstate=0x07E2009052E7E117A305040800002F05 */ ;
    defparam mux_505_Mux_2.initval = 128'h07E2009052E7E117A305040800002F05;
    ROM128X1A mux_505_Mux_3 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2327)) /* synthesis initstate=0x02E7E1B600E2E19B4221280000002621 */ ;
    defparam mux_505_Mux_3.initval = 128'h02E7E1B600E2E19B4221280000002621;
    ROM128X1A mux_505_Mux_4 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2326)) /* synthesis initstate=0x02E3E1B610EAE1972379045800002F79 */ ;
    defparam mux_505_Mux_4.initval = 128'h02E3E1B610EAE1972379045800002F79;
    ROM128X1A mux_505_Mux_5 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2325)) /* synthesis initstate=0x02BAE19E01A8E1870169002000001D69 */ ;
    defparam mux_505_Mux_5.initval = 128'h02BAE19E01A8E1870169002000001D69;
    FD1P3IX cnt_scan_i0_i0 (.D(cnt_scan_4__N_308[0]), .SP(clk_c_enable_19), 
            .CD(n11909), .CK(clk_c), .Q(cnt_scan[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_scan_i0_i0.GSR = "ENABLED";
    FD1P3IX char_i0_i0 (.D(char_167__N_358[0]), .SP(clk_c_enable_59), .CD(n11892), 
            .CK(clk_c), .Q(char[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_189_4_lut (.A(n18396), .B(char[124]), .C(num[3]), 
         .D(num[4]), .Z(n18362)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i1_2_lut_rep_189_4_lut.init = 16'h0080;
    FD1P3IX cnt_i0_i10 (.D(n312), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[10]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i10.GSR = "ENABLED";
    LUT4 i50_4_lut (.A(state_back[1]), .B(n4181), .C(state[3]), .D(n18381), 
         .Z(n31)) /* synthesis lut_function=(!((B (C (D))+!B (C))+!A)) */ ;
    defparam i50_4_lut.init = 16'h0a8a;
    ROM128X1A mux_505_Mux_24 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1196)) /* synthesis initstate=0x001010012C1F82FDC3AD02CC0000FBAD */ ;
    defparam mux_505_Mux_24.initval = 128'h001010012C1F82FDC3AD02CC0000FBAD;
    ROM128X1A mux_505_Mux_25 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1195)) /* synthesis initstate=0x00100040580020020C42001C00000442 */ ;
    defparam mux_505_Mux_25.initval = 128'h00100040580020020C42001C00000442;
    ROM128X1A mux_505_Mux_26 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1194)) /* synthesis initstate=0x041BA2FA090040083C3001AC00000030 */ ;
    defparam mux_505_Mux_26.initval = 128'h041BA2FA090040083C3001AC00000030;
    ROM128X1A mux_505_Mux_27 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1193)) /* synthesis initstate=0x011441441A0D096503402D580000CB40 */ ;
    defparam mux_505_Mux_27.initval = 128'h011441441A0D096503402D580000CB40;
    ROM128X1A mux_505_Mux_28 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1192)) /* synthesis initstate=0x001808620D0000023C91810800000491 */ ;
    defparam mux_505_Mux_28.initval = 128'h001808620D0000023C91810800000491;
    ROM128X1A mux_505_Mux_29 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n1191)) /* synthesis initstate=0x075300C0184000000484403800000084 */ ;
    defparam mux_505_Mux_29.initval = 128'h075300C0184000000484403800000084;
    FD1S3AX num_delay_i5 (.D(num_delay_15__N_231[5]), .CK(clk_c), .Q(num_delay[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i5.GSR = "ENABLED";
    LUT4 i5756_4_lut_4_lut (.A(n18410), .B(n18387), .C(cnt_main[1]), .D(cnt_main[0]), 
         .Z(n14097)) /* synthesis lut_function=(A (B+(C (D)+!C !(D)))+!A !((C+!(D))+!B)) */ ;
    defparam i5756_4_lut_4_lut.init = 16'hac8a;
    LUT4 i5783_3_lut_rep_201_4_lut_3_lut (.A(cnt_main[0]), .B(cnt_main[1]), 
         .C(n18386), .Z(n18374)) /* synthesis lut_function=(A (C)+!A ((C)+!B)) */ ;
    defparam i5783_3_lut_rep_201_4_lut_3_lut.init = 16'hf1f1;
    FD1P3IX cnt_i0_i11 (.D(n311), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[11]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i11.GSR = "ENABLED";
    LUT4 i9121_3_lut (.A(char_reg[5]), .B(char_reg[4]), .C(cnt_write[1]), 
         .Z(n17487)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9121_3_lut.init = 16'hcaca;
    LUT4 i2_3_lut_rep_205 (.A(num[4]), .B(n11097), .C(num[3]), .Z(n18378)) /* synthesis lut_function=(A+((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i2_3_lut_rep_205.init = 16'hfbfb;
    LUT4 i5601_2_lut_rep_188_4_lut (.A(num[4]), .B(n11097), .C(num[3]), 
         .D(char[6]), .Z(n18361)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5601_2_lut_rep_188_4_lut.init = 16'h0400;
    FD1P3AX y_p_i0_i4 (.D(n14161), .SP(clk_c_enable_75), .CK(clk_c), .Q(y_p[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam y_p_i0_i4.GSR = "ENABLED";
    LUT4 n18157_bdd_2_lut_3_lut (.A(n18156), .B(state[3]), .C(state[4]), 
         .Z(n18158)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam n18157_bdd_2_lut_3_lut.init = 16'h0202;
    CCU2D num_1426_add_4_7 (.A0(cnt_scan[3]), .B0(n11418), .C0(num[5]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n11418), .C1(num[6]), 
          .D1(GND_net), .CIN(n15855), .COUT(n15856), .S0(n40), .S1(n39_adj_14));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_add_4_7.INIT0 = 16'he1e1;
    defparam num_1426_add_4_7.INIT1 = 16'he1e1;
    defparam num_1426_add_4_7.INJECT1_0 = "NO";
    defparam num_1426_add_4_7.INJECT1_1 = "NO";
    PFUMX i47 (.BLUT(n6_adj_30), .ALUT(n17216), .C0(state[3]), .Z(n24_adj_29));
    CCU2D add_33_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15833), 
          .COUT(n15834), .S0(n287), .S1(n286));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_11.INIT0 = 16'h5aaa;
    defparam add_33_11.INIT1 = 16'h5aaa;
    defparam add_33_11.INJECT1_0 = "NO";
    defparam add_33_11.INJECT1_1 = "NO";
    OB oled_rst_pad (.I(oled_rst_c), .O(oled_rst));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(33[15:23])
    LUT4 i9120_3_lut (.A(char_reg[7]), .B(char_reg[6]), .C(cnt_write[1]), 
         .Z(n17486)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9120_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_4_lut_4_lut (.A(state[0]), .B(state[3]), .C(state[2]), 
         .D(state[4]), .Z(n47)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B (C+(D))+!B (C (D)+!C !(D))))) */ ;
    defparam i1_4_lut_4_lut_4_lut.init = 16'h0116;
    CCU2D add_33_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15832), 
          .COUT(n15833), .S0(n289), .S1(n288));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_9.INIT0 = 16'h5aaa;
    defparam add_33_9.INIT1 = 16'h5aaa;
    defparam add_33_9.INJECT1_0 = "NO";
    defparam add_33_9.INJECT1_1 = "NO";
    LUT4 i1_2_lut_4_lut (.A(state[2]), .B(n17962), .C(char_reg[5]), .D(n18345), 
         .Z(n6_adj_62)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_2_lut_4_lut.init = 16'ha088;
    LUT4 hour_h_c_2_bdd_3_lut_9462 (.A(temp_h_c_2), .B(hour_l_c_2), .C(cnt_main[2]), 
         .Z(n17766)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam hour_h_c_2_bdd_3_lut_9462.init = 16'hacac;
    LUT4 i35_4_lut_4_lut (.A(state[4]), .B(n18391), .C(state_back[4]), 
         .D(state[5]), .Z(n16_adj_75)) /* synthesis lut_function=(!(A (B+(D))+!A !(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i35_4_lut_4_lut.init = 16'h5022;
    LUT4 i5602_2_lut_rep_190_4_lut (.A(num[4]), .B(n11097), .C(num[3]), 
         .D(char[0]), .Z(n18363)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5602_2_lut_rep_190_4_lut.init = 16'h0400;
    LUT4 i92_4_lut (.A(n15863), .B(n7_adj_96), .C(cnt_scan[1]), .D(n8_adj_95), 
         .Z(n57)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam i92_4_lut.init = 16'hca0a;
    LUT4 i9256_2_lut_2_lut (.A(n18346), .B(n67), .Z(n12265)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i9256_2_lut_2_lut.init = 16'h4444;
    LUT4 mux_369_Mux_3_i31_3_lut (.A(n14143), .B(char_reg[3]), .C(n18345), 
         .Z(n3781)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam mux_369_Mux_3_i31_3_lut.init = 16'hc5c5;
    LUT4 i2046_2_lut_rep_167_4_lut (.A(n18373), .B(state[4]), .C(state[5]), 
         .D(n2405), .Z(n18340)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i2046_2_lut_rep_167_4_lut.init = 16'hffef;
    PFUMX i9125 (.BLUT(n17488), .ALUT(n17489), .C0(cnt_write[2]), .Z(n17491));
    LUT4 i1_4_lut (.A(state[2]), .B(n17997), .C(char_reg[4]), .D(n18345), 
         .Z(n6_adj_55)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut.init = 16'ha088;
    LUT4 i2_3_lut_rep_172_4_lut (.A(n18395), .B(cnt_init[0]), .C(oled_dcn_N_650), 
         .D(n18402), .Z(n18345)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2_3_lut_rep_172_4_lut.init = 16'hfffe;
    LUT4 state_0__bdd_4_lut_9613_rep_186 (.A(state[0]), .B(n11_adj_86), 
         .C(n18389), .D(n18415), .Z(clk_c_enable_19)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B+!(C+!(D))))) */ ;
    defparam state_0__bdd_4_lut_9613_rep_186.init = 16'h3a33;
    LUT4 hour_h_c_2_bdd_2_lut_9461 (.A(hour_h_c_2), .B(cnt_main[2]), .Z(n17767)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam hour_h_c_2_bdd_2_lut_9461.init = 16'h2222;
    LUT4 num_1426_mux_6_i5_4_lut (.A(n18374), .B(n41), .C(state[3]), .D(state[0]), 
         .Z(n51)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_mux_6_i5_4_lut.init = 16'hc0c5;
    LUT4 mux_65_i2_4_lut (.A(n445), .B(n458), .C(n9_adj_4), .D(n18375), 
         .Z(cnt_scan_4__N_308[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(120[16] 121[40])
    defparam mux_65_i2_4_lut.init = 16'hca0a;
    LUT4 i3_4_lut (.A(cnt_scan[0]), .B(cnt_scan[2]), .C(cnt_scan[4]), 
         .D(cnt_scan[1]), .Z(n11418)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(136[8:13])
    defparam i3_4_lut.init = 16'hfdff;
    PFUMX i9315 (.BLUT(n17787), .ALUT(n17786), .C0(cnt_main[2]), .Z(n17788));
    LUT4 i1748_2_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .Z(n458)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(121[24:39])
    defparam i1748_2_lut.init = 16'h6666;
    LUT4 i5688_2_lut (.A(cnt_scan[2]), .B(cnt_scan[3]), .Z(n14025)) /* synthesis lut_function=(A (B)) */ ;
    defparam i5688_2_lut.init = 16'h8888;
    LUT4 mux_1161_i1_3_lut (.A(min_l_c_0), .B(temp_p_c_0), .C(cnt_main[2]), 
         .Z(n8016)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_1161_i1_3_lut.init = 16'hcaca;
    ROM128X1A mux_505_Mux_32 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n818)) /* synthesis initstate=0x0000090417F5797C00A800000000E8A8 */ ;
    defparam mux_505_Mux_32.initval = 128'h0000090417F5797C00A800000000E8A8;
    ROM128X1A mux_505_Mux_33 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n817)) /* synthesis initstate=0x0000090403EFF9FD832500600000FB25 */ ;
    defparam mux_505_Mux_33.initval = 128'h0000090403EFF9FD832500600000FB25;
    ROM128X1A mux_505_Mux_34 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n816)) /* synthesis initstate=0x07F5690452EFF9FE236104580000FF61 */ ;
    defparam mux_505_Mux_34.initval = 128'h07F5690452EFF9FE236104580000FF61;
    ROM128X1A mux_505_Mux_35 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n815)) /* synthesis initstate=0x02EFE9FC00E7F9F6105128000000FC51 */ ;
    defparam mux_505_Mux_35.initval = 128'h02EFE9FC00E7F9F6105128000000FC51;
    ROM128X1A mux_505_Mux_36 (.AD0(n18363), .AD1(n18353), .AD2(n647), 
            .AD3(n18352), .AD4(n18362), .AD5(n18397), .AD6(n18361), 
            .DO0(n814)) /* synthesis initstate=0x02E7E9BC10E7F9F7215104480000FD51 */ ;
    defparam mux_505_Mux_36.initval = 128'h02E7E9BC10E7F9F7215104480000FD51;
    FD1P3IX cnt_init_i0_i3 (.D(n246), .SP(clk_c_enable_55), .CD(n12265), 
            .CK(clk_c), .Q(cnt_init[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_init_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_i0_i1 (.D(n321), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i1.GSR = "ENABLED";
    LUT4 i3489_3_lut_4_lut_4_lut (.A(n18355), .B(n18376), .C(n18354), 
         .D(n18393), .Z(n11847)) /* synthesis lut_function=(!(A+!(B (D)+!B (C (D))))) */ ;
    defparam i3489_3_lut_4_lut_4_lut.init = 16'h5400;
    LUT4 mux_65_i1_4_lut (.A(n445), .B(cnt_scan[0]), .C(n9_adj_4), .D(n18375), 
         .Z(cnt_scan_4__N_308[0])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(120[16] 121[40])
    defparam mux_65_i1_4_lut.init = 16'h3a0a;
    LUT4 i3551_2_lut_4_lut (.A(state[0]), .B(n11_adj_86), .C(n18389), 
         .D(n18415), .Z(n11909)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam i3551_2_lut_4_lut.init = 16'h0800;
    FD1P3IX cnt_i0_i2 (.D(n320), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i2.GSR = "ENABLED";
    ROM128X1A mux_505_Mux_0 (.AD0(n18363), .AD1(n18353), .AD2(n647), .AD3(n18352), 
            .AD4(n18362), .AD5(n18397), .AD6(n18361), .DO0(n2330)) /* synthesis initstate=0x0000001017F86D6000A800200000C0A8 */ ;
    defparam mux_505_Mux_0.initval = 128'h0000001017F86D6000A800200000C0A8;
    LUT4 i5670_2_lut (.A(n286), .B(oled_dcn_N_650), .Z(n312)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5670_2_lut.init = 16'h2222;
    LUT4 i3549_2_lut_3_lut_4_lut (.A(state[2]), .B(n18399), .C(clk_c_enable_73), 
         .D(n18389), .Z(n11894)) /* synthesis lut_function=(A (B (C)+!B (C (D)))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(97[5:9])
    defparam i3549_2_lut_3_lut_4_lut.init = 16'hf0d0;
    FD1P3IX cnt_delay_i0_i15 (.D(n2408), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[15]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i15.GSR = "ENABLED";
    PFUMX i47_adj_2 (.BLUT(n6_adj_57), .ALUT(n12_adj_58), .C0(state[3]), 
          .Z(n24));
    LUT4 i1_4_lut_adj_3 (.A(state[0]), .B(num_delay[5]), .C(n16_adj_23), 
         .D(n19_adj_42), .Z(num_delay_15__N_231[5])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_3.init = 16'hdc50;
    FD1P3IX cnt_i0_i12 (.D(n310), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[12]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i12.GSR = "ENABLED";
    LUT4 i4176_4_lut (.A(num_delay[5]), .B(num_delay_15__N_542[5]), .C(state[2]), 
         .D(n14000), .Z(n16_adj_23)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i4176_4_lut.init = 16'h0aca;
    LUT4 i1_4_lut_adj_4 (.A(n18360), .B(num_delay[5]), .C(n17267), .D(n18379), 
         .Z(num_delay_15__N_542[5])) /* synthesis lut_function=(A+(B (C+(D)))) */ ;
    defparam i1_4_lut_adj_4.init = 16'heeea;
    FD1P3IX cnt_i0_i3 (.D(n319), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i3.GSR = "ENABLED";
    LUT4 i2_4_lut_rep_173_4_lut (.A(n18415), .B(n18380), .C(n4), .D(n11202), 
         .Z(n18346)) /* synthesis lut_function=(A (C+(D))+!A (B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i2_4_lut_rep_173_4_lut.init = 16'hfff4;
    FD1P3IX cnt_i0_i13 (.D(n309), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[13]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i13.GSR = "ENABLED";
    FD1P3AX oled_dat_313 (.D(n17202), .SP(clk_c_enable_31), .CK(clk_c), 
            .Q(oled_dat_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam oled_dat_313.GSR = "ENABLED";
    LUT4 i5669_2_lut (.A(n285), .B(oled_dcn_N_650), .Z(n311)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5669_2_lut.init = 16'h2222;
    LUT4 i5482_2_lut (.A(n295), .B(oled_dcn_N_650), .Z(n321)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5482_2_lut.init = 16'h2222;
    FD1P3IX cnt_delay_i0_i6 (.D(n2417), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i6.GSR = "ENABLED";
    FD1P3IX cnt_i0_i4 (.D(n318), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i4.GSR = "ENABLED";
    FD1P3IX cnt_i0_i14 (.D(n308), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[14]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i14.GSR = "ENABLED";
    FD1P3IX cnt_i0_i15 (.D(n307), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[15]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i15.GSR = "ENABLED";
    FD1P3AY oled_clk_312 (.D(n5285), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(oled_clk_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam oled_clk_312.GSR = "ENABLED";
    FD1P3AX oled_dcn_311 (.D(n17273), .SP(clk_c_enable_37), .CK(clk_c), 
            .Q(oled_dcn_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam oled_dcn_311.GSR = "ENABLED";
    FD1P3AY oled_rst_310 (.D(n5222), .SP(clk_c_enable_38), .CK(clk_c), 
            .Q(oled_rst_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam oled_rst_310.GSR = "ENABLED";
    PFUMX i9664 (.BLUT(n18425), .ALUT(n18426), .C0(cnt_scan[1]), .Z(n18427));
    PFUMX i9454 (.BLUT(n18035), .ALUT(n18034), .C0(cnt_scan[1]), .Z(n18036));
    FD1P3AX char_i0_i123 (.D(n9122), .SP(clk_c_enable_59), .CK(clk_c), 
            .Q(char[123]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i123.GSR = "ENABLED";
    LUT4 i5472_2_lut (.A(n294), .B(oled_dcn_N_650), .Z(n320)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5472_2_lut.init = 16'h2222;
    LUT4 i5666_2_lut (.A(n284), .B(oled_dcn_N_650), .Z(n310)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5666_2_lut.init = 16'h2222;
    LUT4 i5471_2_lut (.A(n293), .B(oled_dcn_N_650), .Z(n319)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5471_2_lut.init = 16'h2222;
    LUT4 n18037_bdd_3_lut_9601 (.A(n1194), .B(n1572), .C(cnt_scan[0]), 
         .Z(n18110)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n18037_bdd_3_lut_9601.init = 16'hcaca;
    LUT4 i5665_2_lut (.A(n283), .B(oled_dcn_N_650), .Z(n309)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5665_2_lut.init = 16'h2222;
    LUT4 i2_4_lut (.A(n15892), .B(n12270), .C(state[0]), .D(n18366), 
         .Z(clk_c_enable_31)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;
    defparam i2_4_lut.init = 16'hc088;
    LUT4 i2_3_lut (.A(oled_csn_N_634), .B(state[4]), .C(cnt_write[0]), 
         .Z(n15892)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i2_3_lut.init = 16'h4040;
    LUT4 i1_3_lut (.A(state[4]), .B(oled_dat_N_672), .C(n18366), .Z(n17202)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_3_lut.init = 16'h0808;
    LUT4 i1_2_lut_3_lut_4_lut (.A(n18411), .B(n18399), .C(n39), .D(n18400), 
         .Z(clk_c_enable_36)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ;
    defparam i1_2_lut_3_lut_4_lut.init = 16'he0f0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n18411), .B(n18399), .C(n5296), 
         .D(n18400), .Z(n12270)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'he0f0;
    OB oled_csn_pad (.I(oled_csn_c), .O(oled_csn));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(32[15:23])
    PFUMX i47_adj_6 (.BLUT(n6_adj_60), .ALUT(n17217), .C0(state[3]), .Z(n24_adj_59));
    LUT4 mux_1161_i4_3_lut (.A(min_l_c_3), .B(temp_p_c_3), .C(cnt_main[2]), 
         .Z(n8013)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_1161_i4_3_lut.init = 16'hcaca;
    PFUMX i74 (.BLUT(n34_adj_84), .ALUT(n41_adj_83), .C0(state[5]), .Z(n50));
    FD1P3AX char_i0_i6 (.D(n17220), .SP(clk_c_enable_59), .CK(clk_c), 
            .Q(char[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i6.GSR = "ENABLED";
    LUT4 mux_1161_i3_3_lut (.A(min_l_c_2), .B(temp_p_c_2), .C(cnt_main[2]), 
         .Z(n8014)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_1161_i3_3_lut.init = 16'hcaca;
    FD1P3AX char_i0_i5 (.D(n9238), .SP(clk_c_enable_59), .CK(clk_c), .Q(char[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i5.GSR = "ENABLED";
    LUT4 n8010_bdd_4_lut (.A(cnt_main[0]), .B(n18413), .C(temp_h_c_1), 
         .D(temp_l_c_1), .Z(n17760)) /* synthesis lut_function=(!(A (B+!(C))+!A !((D)+!B))) */ ;
    defparam n8010_bdd_4_lut.init = 16'h7531;
    LUT4 n816_bdd_4_lut_9604 (.A(n816), .B(cnt_scan[0]), .C(cnt_scan[2]), 
         .D(x_ph[2]), .Z(n18113)) /* synthesis lut_function=(A (B (C)+!B !(C+!(D)))+!A !(B+(C+!(D)))) */ ;
    defparam n816_bdd_4_lut_9604.init = 16'h8380;
    LUT4 mux_1161_i2_3_lut (.A(min_l_c_1), .B(temp_p_c_1), .C(cnt_main[2]), 
         .Z(n8015)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam mux_1161_i2_3_lut.init = 16'hcaca;
    LUT4 i9123_3_lut (.A(char_reg[1]), .B(char_reg[0]), .C(cnt_write[1]), 
         .Z(n17489)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9123_3_lut.init = 16'hcaca;
    LUT4 i5691_2_lut (.A(n292), .B(oled_dcn_N_650), .Z(n318)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5691_2_lut.init = 16'h2222;
    LUT4 n3446_bdd_2_lut_9525 (.A(n18113), .B(cnt_scan[1]), .Z(n18114)) /* synthesis lut_function=(A (B)) */ ;
    defparam n3446_bdd_2_lut_9525.init = 16'h8888;
    LUT4 n18725_bdd_2_lut_4_lut (.A(n18724), .B(n18721), .C(state[2]), 
         .D(state[3]), .Z(n18726)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n18725_bdd_2_lut_4_lut.init = 16'h00ca;
    LUT4 i1_4_lut_4_lut_adj_7 (.A(n18395), .B(n18402), .C(oled_dcn_N_650), 
         .D(num_delay[0]), .Z(n15_adj_5)) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B ((D)+!C))) */ ;
    defparam i1_4_lut_4_lut_adj_7.init = 16'hdd01;
    LUT4 i9243_2_lut_3_lut_4_lut_4_lut (.A(n18355), .B(n18393), .C(n18348), 
         .D(n14097), .Z(clk_c_enable_79)) /* synthesis lut_function=(!(A+((C (D))+!B))) */ ;
    defparam i9243_2_lut_3_lut_4_lut_4_lut.init = 16'h0444;
    LUT4 i1_4_lut_adj_8 (.A(state[2]), .B(n18360), .C(n19_adj_72), .D(n16_adj_71), 
         .Z(n6_adj_33)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i1_4_lut_adj_8.init = 16'haaa8;
    LUT4 i1_3_lut_4_lut_adj_9 (.A(cnt_init[0]), .B(n18394), .C(n18383), 
         .D(num_delay[3]), .Z(n4_adj_87)) /* synthesis lut_function=(A ((C (D))+!B)+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_3_lut_4_lut_adj_9.init = 16'hf222;
    FD1P3AX cnt_init_i0_i0 (.D(n15910), .SP(clk_c_enable_55), .CK(clk_c), 
            .Q(cnt_init[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_init_i0_i0.GSR = "ENABLED";
    LUT4 i1_3_lut_4_lut_adj_10 (.A(cnt_init[0]), .B(n18394), .C(n18383), 
         .D(num_delay[14]), .Z(n4_adj_94)) /* synthesis lut_function=(A ((C (D))+!B)+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_3_lut_4_lut_adj_10.init = 16'hf222;
    PFUMX i44 (.BLUT(n28), .ALUT(n25), .C0(n17444), .Z(n23));
    FD1P3IX cnt_delay_i0_i7 (.D(n2416), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[7]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i7.GSR = "ENABLED";
    LUT4 i5655_2_lut (.A(n282), .B(oled_dcn_N_650), .Z(n308)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5655_2_lut.init = 16'h2222;
    PFUMX i9312 (.BLUT(n17783), .ALUT(n17778), .C0(n7267), .Z(char_167__N_358[3]));
    LUT4 i8991_2_lut_4_lut_4_lut (.A(n18395), .B(n18402), .C(state_back[5]), 
         .D(oled_dcn_N_650), .Z(n17353)) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (C (D)))) */ ;
    defparam i8991_2_lut_4_lut_4_lut.init = 16'hd0c0;
    CCU2D num_1426_add_4_5 (.A0(cnt_scan[3]), .B0(n11418), .C0(num[3]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n11418), .C1(num[4]), 
          .D1(GND_net), .CIN(n15854), .COUT(n15855), .S0(n42), .S1(n41));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_add_4_5.INIT0 = 16'he1e1;
    defparam num_1426_add_4_5.INIT1 = 16'he1e1;
    defparam num_1426_add_4_5.INJECT1_0 = "NO";
    defparam num_1426_add_4_5.INJECT1_1 = "NO";
    LUT4 i1_4_lut_4_lut_adj_11 (.A(n18395), .B(n18402), .C(oled_dcn_N_650), 
         .D(num_delay[2]), .Z(n15)) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B ((D)+!C))) */ ;
    defparam i1_4_lut_4_lut_adj_11.init = 16'hdd01;
    LUT4 i9044_4_lut (.A(n9_adj_27), .B(state[0]), .C(n18374), .D(state[3]), 
         .Z(n37)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B+(D)))) */ ;
    defparam i9044_4_lut.init = 16'h0013;
    CCU2D add_33_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15831), 
          .COUT(n15832), .S0(n291), .S1(n290));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_7.INIT0 = 16'h5aaa;
    defparam add_33_7.INIT1 = 16'h5aaa;
    defparam add_33_7.INJECT1_0 = "NO";
    defparam add_33_7.INJECT1_1 = "NO";
    CCU2D add_33_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n15829), 
          .S1(n296));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_1.INIT0 = 16'hF000;
    defparam add_33_1.INIT1 = 16'h5555;
    defparam add_33_1.INJECT1_0 = "NO";
    defparam add_33_1.INJECT1_1 = "NO";
    CCU2D num_1426_add_4_3 (.A0(cnt_scan[3]), .B0(n11418), .C0(num[1]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n11418), .C1(num[2]), 
          .D1(GND_net), .CIN(n15853), .COUT(n15854), .S0(n44), .S1(n43));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_add_4_3.INIT0 = 16'he1e1;
    defparam num_1426_add_4_3.INIT1 = 16'he1e1;
    defparam num_1426_add_4_3.INJECT1_0 = "NO";
    defparam num_1426_add_4_3.INJECT1_1 = "NO";
    CCU2D add_33_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15830), 
          .COUT(n15831), .S0(n293), .S1(n292));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_5.INIT0 = 16'h5aaa;
    defparam add_33_5.INIT1 = 16'h5aaa;
    defparam add_33_5.INJECT1_0 = "NO";
    defparam add_33_5.INJECT1_1 = "NO";
    CCU2D add_107_11 (.A0(cnt_delay[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15841), .COUT(n15842), .S0(n2414), .S1(n2413));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_11.INIT0 = 16'h5aaa;
    defparam add_107_11.INIT1 = 16'h5aaa;
    defparam add_107_11.INJECT1_0 = "NO";
    defparam add_107_11.INJECT1_1 = "NO";
    CCU2D add_107_9 (.A0(cnt_delay[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15840), .COUT(n15841), .S0(n2416), .S1(n2415));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_9.INIT0 = 16'h5aaa;
    defparam add_107_9.INIT1 = 16'h5aaa;
    defparam add_107_9.INJECT1_0 = "NO";
    defparam add_107_9.INJECT1_1 = "NO";
    CCU2D add_33_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15829), 
          .COUT(n15830), .S0(n295), .S1(n294));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_3.INIT0 = 16'h5aaa;
    defparam add_33_3.INIT1 = 16'h5aaa;
    defparam add_33_3.INJECT1_0 = "NO";
    defparam add_33_3.INJECT1_1 = "NO";
    CCU2D add_107_7 (.A0(cnt_delay[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15839), .COUT(n15840), .S0(n2418), .S1(n2417));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_7.INIT0 = 16'h5aaa;
    defparam add_107_7.INIT1 = 16'h5aaa;
    defparam add_107_7.INJECT1_0 = "NO";
    defparam add_107_7.INJECT1_1 = "NO";
    LUT4 i5648_2_lut (.A(n281), .B(oled_dcn_N_650), .Z(n307)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5648_2_lut.init = 16'h2222;
    FD1P3AX num_1426__i0 (.D(n55), .SP(clk_c_enable_72), .CK(clk_c), .Q(num[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i0.GSR = "ENABLED";
    LUT4 i60_2_lut (.A(state[3]), .B(state[0]), .Z(n33_adj_92)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i60_2_lut.init = 16'h6666;
    LUT4 i8967_2_lut_4_lut_4_lut (.A(n18395), .B(n18402), .C(state_back[0]), 
         .D(oled_dcn_N_650), .Z(n17313)) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B (C (D)))) */ ;
    defparam i8967_2_lut_4_lut_4_lut.init = 16'hd0c0;
    CCU2D add_107_5 (.A0(cnt_delay[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15838), .COUT(n15839), .S0(n2420), .S1(n2419));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_5.INIT0 = 16'h5aaa;
    defparam add_107_5.INIT1 = 16'h5aaa;
    defparam add_107_5.INJECT1_0 = "NO";
    defparam add_107_5.INJECT1_1 = "NO";
    FD1P3IX cnt_main_i0_i2 (.D(cnt_main_4__N_298[2]), .SP(clk_c_enable_76), 
            .CD(n11846), .CK(clk_c), .Q(cnt_main[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_main_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i4 (.D(n7), .SP(clk_c_enable_76), .CD(n11847), 
            .CK(clk_c), .Q(cnt_main[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_main_i0_i4.GSR = "ENABLED";
    FD1P3IX state_i0_i2 (.D(n16110), .SP(clk_c_enable_84), .CD(n11842), 
            .CK(clk_c), .Q(state[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i2.GSR = "ENABLED";
    GSR GSR_INST (.GSR(rst_n_c));
    FD1P3IX state_i0_i3 (.D(n18158), .SP(clk_c_enable_84), .CD(n11842), 
            .CK(clk_c), .Q(state[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i3.GSR = "ENABLED";
    FD1P3IX state_i0_i4 (.D(n16300), .SP(clk_c_enable_84), .CD(n14137), 
            .CK(clk_c), .Q(state[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i4.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_12 (.A(n24_adj_67), .B(char_reg[7]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[7])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_12.init = 16'hce0a;
    TSALL TSALL_INST (.TSALL(GND_net));
    CCU2D num_1426_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n11418), .C1(num[0]), 
          .D1(GND_net), .COUT(n15853), .S1(n45_adj_34));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_add_4_1.INIT0 = 16'hF000;
    defparam num_1426_add_4_1.INIT1 = 16'he1e1;
    defparam num_1426_add_4_1.INJECT1_0 = "NO";
    defparam num_1426_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_3_lut_4_lut_adj_13 (.A(n18395), .B(n18402), .C(oled_dcn_N_650), 
         .D(state_back[2]), .Z(n11507)) /* synthesis lut_function=(!(A+(B+!((D)+!C)))) */ ;
    defparam i1_3_lut_4_lut_adj_13.init = 16'h1101;
    PFUMX i9431 (.BLUT(n18007), .ALUT(n18006), .C0(cnt_scan[3]), .Z(n18008));
    CCU2D add_107_3 (.A0(cnt_delay[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15837), .COUT(n15838), .S0(n2422), .S1(n2421));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_3.INIT0 = 16'h5aaa;
    defparam add_107_3.INIT1 = 16'h5aaa;
    defparam add_107_3.INJECT1_0 = "NO";
    defparam add_107_3.INJECT1_1 = "NO";
    CCU2D sub_1103_add_2_17 (.A0(cnt_delay[15]), .B0(num_delay[15]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15852), .S1(n2405));
    defparam sub_1103_add_2_17.INIT0 = 16'h5999;
    defparam sub_1103_add_2_17.INIT1 = 16'h0000;
    defparam sub_1103_add_2_17.INJECT1_0 = "NO";
    defparam sub_1103_add_2_17.INJECT1_1 = "NO";
    LUT4 i77_3_lut_4_lut (.A(cnt_init[2]), .B(n18395), .C(cnt_init[0]), 
         .D(n18347), .Z(n81)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+!(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[22:30])
    defparam i77_3_lut_4_lut.init = 16'hefec;
    LUT4 n17494_bdd_3_lut_9562 (.A(n1190), .B(n1568), .C(cnt_scan[0]), 
         .Z(n18124)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17494_bdd_3_lut_9562.init = 16'hcaca;
    LUT4 i9100_3_lut (.A(n1952), .B(n2330), .C(cnt_scan[0]), .Z(n17466)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9100_3_lut.init = 16'hcaca;
    LUT4 i5677_2_lut_rep_179 (.A(n2132), .B(num[4]), .Z(n18352)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5677_2_lut_rep_179.init = 16'h2222;
    LUT4 mux_929_i1_4_lut (.A(oled_clk_N_670), .B(state[0]), .C(n18366), 
         .D(state[4]), .Z(n5285)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam mux_929_i1_4_lut.init = 16'hcac0;
    LUT4 cnt_write_4__I_0_361_i31_3_lut (.A(cnt_write[0]), .B(oled_csn_N_634), 
         .C(n18414), .Z(oled_clk_N_670)) /* synthesis lut_function=(!(A+(B (C)+!B !(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(143[7] 163[14])
    defparam cnt_write_4__I_0_361_i31_3_lut.init = 16'h1414;
    LUT4 i1_2_lut_4_lut_adj_14 (.A(n18163), .B(n3778), .C(n17422), .D(state[2]), 
         .Z(n6_adj_65)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_14.init = 16'hac00;
    FD1P3IX char_i0_i1 (.D(char_167__N_358[1]), .SP(clk_c_enable_59), .CD(n11892), 
            .CK(clk_c), .Q(char[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut_adj_15 (.A(cnt_init[2]), .B(n18395), .C(cnt_init[0]), 
         .D(state_back[2]), .Z(n19_adj_72)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[22:30])
    defparam i1_2_lut_4_lut_adj_15.init = 16'hec00;
    LUT4 i1_2_lut (.A(cnt_scan[0]), .B(cnt_scan[2]), .Z(n17259)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i1_4_lut_adj_16 (.A(n24_adj_64), .B(char_reg[6]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[6])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_16.init = 16'hce0a;
    LUT4 i1_2_lut_4_lut_adj_17 (.A(cnt_init[2]), .B(n18395), .C(cnt_init[0]), 
         .D(state_back[0]), .Z(n19_adj_78)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[22:30])
    defparam i1_2_lut_4_lut_adj_17.init = 16'hec00;
    FD1P3IX char_i0_i2 (.D(char_167__N_358[2]), .SP(clk_c_enable_59), .CD(n11892), 
            .CK(clk_c), .Q(char[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_i0_i5 (.D(n317), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i5.GSR = "ENABLED";
    PFUMX i9428 (.BLUT(n18004), .ALUT(n17466), .C0(cnt_scan[1]), .Z(n18005));
    LUT4 i1_4_lut_adj_18 (.A(n5296), .B(n18204), .C(n4_adj_53), .D(n17272), 
         .Z(clk_c_enable_37)) /* synthesis lut_function=(!((B ((D)+!C)+!B !(C))+!A)) */ ;
    defparam i1_4_lut_adj_18.init = 16'h20a0;
    LUT4 i1_2_lut_4_lut_adj_19 (.A(cnt_init[2]), .B(n18395), .C(cnt_init[0]), 
         .D(state_back[5]), .Z(n19_adj_13)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(49[22:30])
    defparam i1_2_lut_4_lut_adj_19.init = 16'hec00;
    LUT4 i12_4_lut (.A(n8230), .B(n18345), .C(n18365), .D(state[2]), 
         .Z(n16826)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ;
    defparam i12_4_lut.init = 16'h3afa;
    FD1P3IX char_i0_i3 (.D(char_167__N_358[3]), .SP(clk_c_enable_59), .CD(n11892), 
            .CK(clk_c), .Q(char[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i3.GSR = "ENABLED";
    LUT4 n7267_bdd_3_lut_9300 (.A(cnt_main[0]), .B(n8015), .C(min_h_c_1), 
         .Z(n17759)) /* synthesis lut_function=(A (B)+!A (C)) */ ;
    defparam n7267_bdd_3_lut_9300.init = 16'hd8d8;
    LUT4 n17768_bdd_3_lut (.A(n17768), .B(n17765), .C(n18413), .Z(n17769)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17768_bdd_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_20 (.A(cnt_scan[3]), .B(n17272), .C(cnt_scan[2]), 
         .Z(n17273)) /* synthesis lut_function=(!(A ((C)+!B)+!A !(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_adj_20.init = 16'h4848;
    FD1P3IX cnt_i0_i0 (.D(n322), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_init_i0_i4 (.D(n245), .SP(clk_c_enable_55), .CD(n12265), 
            .CK(clk_c), .Q(cnt_init[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_init_i0_i4.GSR = "ENABLED";
    LUT4 i9015_4_lut (.A(n5296), .B(n8230), .C(n17275), .D(n18365), 
         .Z(clk_c_enable_38)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i9015_4_lut.init = 16'ha088;
    CCU2D sub_1103_add_2_15 (.A0(cnt_delay[13]), .B0(num_delay[13]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[14]), .B1(num_delay[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15851), .COUT(n15852));
    defparam sub_1103_add_2_15.INIT0 = 16'h5999;
    defparam sub_1103_add_2_15.INIT1 = 16'h5999;
    defparam sub_1103_add_2_15.INJECT1_0 = "NO";
    defparam sub_1103_add_2_15.INJECT1_1 = "NO";
    PFUMX i9425 (.BLUT(n18000), .ALUT(n17999), .C0(cnt_scan[0]), .Z(n18001));
    FD1P3IX char_i0_i122 (.D(n11759), .SP(clk_c_enable_59), .CD(n11888), 
            .CK(clk_c), .Q(char[122]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i122.GSR = "ENABLED";
    FD1P3IX num_1426__i1 (.D(n44), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i1.GSR = "ENABLED";
    FD1P3IX cnt_i0_i6 (.D(n316), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i6.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_21 (.A(n24_adj_61), .B(char_reg[5]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[5])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_21.init = 16'hce0a;
    CCU2D add_107_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n15837), .S1(n2423));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_1.INIT0 = 16'hF000;
    defparam add_107_1.INIT1 = 16'h5555;
    defparam add_107_1.INJECT1_0 = "NO";
    defparam add_107_1.INJECT1_1 = "NO";
    CCU2D sub_1103_add_2_13 (.A0(cnt_delay[11]), .B0(num_delay[11]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[12]), .B1(num_delay[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15850), .COUT(n15851));
    defparam sub_1103_add_2_13.INIT0 = 16'h5999;
    defparam sub_1103_add_2_13.INIT1 = 16'h5999;
    defparam sub_1103_add_2_13.INJECT1_0 = "NO";
    defparam sub_1103_add_2_13.INJECT1_1 = "NO";
    CCU2D add_33_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15836), 
          .S0(n281));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_17.INIT0 = 16'h5aaa;
    defparam add_33_17.INIT1 = 16'h0000;
    defparam add_33_17.INJECT1_0 = "NO";
    defparam add_33_17.INJECT1_1 = "NO";
    FD1P3IX char_i0_i124 (.D(n11759), .SP(clk_c_enable_59), .CD(n11887), 
            .CK(clk_c), .Q(char[124]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam char_i0_i124.GSR = "ENABLED";
    FD1P3IX num_1426__i2 (.D(n43), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i2.GSR = "ENABLED";
    FD1S3AX num_delay_i15 (.D(num_delay_15__N_231[15]), .CK(clk_c), .Q(num_delay[15]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i15.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i1 (.D(n2387), .SP(clk_c_enable_83), .CD(n11884), 
            .CK(clk_c), .Q(cnt_write[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_write_i0_i1.GSR = "ENABLED";
    FD1P3IX num_1426__i3 (.D(n42), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i3.GSR = "ENABLED";
    LUT4 i9091_3_lut (.A(n1948), .B(n2326), .C(cnt_scan[0]), .Z(n17457)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9091_3_lut.init = 16'hcaca;
    LUT4 mux_881_i1_4_lut (.A(n8230), .B(cnt_init[1]), .C(n18365), .D(n17275), 
         .Z(n5222)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam mux_881_i1_4_lut.init = 16'hca0a;
    FD1P3IX num_1426__i5 (.D(n40), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i5.GSR = "ENABLED";
    LUT4 i9208_3_lut_4_lut (.A(state_back[1]), .B(n18401), .C(state[3]), 
         .D(n10_adj_1), .Z(n25)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i9208_3_lut_4_lut.init = 16'hf202;
    LUT4 i9090_3_lut (.A(n1192), .B(n1570), .C(cnt_scan[0]), .Z(n17456)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9090_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_187_3_lut_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), 
         .C(cnt_init[0]), .D(cnt_init[2]), .Z(n18360)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i1_2_lut_rep_187_3_lut_4_lut.init = 16'h0010;
    PFUMX i49 (.BLUT(n28_adj_73), .ALUT(n33), .C0(n17454), .Z(n31_adj_76));
    LUT4 i2_3_lut_4_lut_4_lut (.A(char[0]), .B(n18378), .C(n18080), .D(char[6]), 
         .Z(n17255)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i2_3_lut_4_lut_4_lut.init = 16'h2000;
    LUT4 n17494_bdd_4_lut_9566 (.A(n812), .B(cnt_scan[1]), .C(cnt_scan[2]), 
         .D(cnt_scan[0]), .Z(n18127)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam n17494_bdd_4_lut_9566.init = 16'h8000;
    PFUMX i9298 (.BLUT(n17761), .ALUT(n17760), .C0(cnt_main[2]), .Z(n17762));
    FD1P3IX num_1426__i6 (.D(n39_adj_14), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i6.GSR = "ENABLED";
    PFUMX i9423 (.BLUT(n17996), .ALUT(n17995), .C0(cnt[4]), .Z(n17997));
    FD1S3AX num_delay_i14 (.D(num_delay_15__N_231[14]), .CK(clk_c), .Q(num_delay[14]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i14.GSR = "ENABLED";
    FD1S3AX num_delay_i13 (.D(num_delay_15__N_231[13]), .CK(clk_c), .Q(num_delay[13]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i13.GSR = "ENABLED";
    FD1S3AX num_delay_i12 (.D(num_delay_15__N_231[12]), .CK(clk_c), .Q(num_delay[12]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i12.GSR = "ENABLED";
    FD1S3AX num_delay_i11 (.D(num_delay_15__N_231[11]), .CK(clk_c), .Q(num_delay[11]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i11.GSR = "ENABLED";
    FD1S3AX num_delay_i10 (.D(num_delay_15__N_231[10]), .CK(clk_c), .Q(num_delay[10]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i10.GSR = "ENABLED";
    FD1S3AX num_delay_i9 (.D(num_delay_15__N_231[9]), .CK(clk_c), .Q(num_delay[9]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i9.GSR = "ENABLED";
    FD1S3AX num_delay_i8 (.D(num_delay_15__N_231[8]), .CK(clk_c), .Q(num_delay[8]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i8.GSR = "ENABLED";
    FD1S3AX num_delay_i7 (.D(num_delay_15__N_231[7]), .CK(clk_c), .Q(num_delay[7]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i7.GSR = "ENABLED";
    FD1S3AX num_delay_i6 (.D(num_delay_15__N_231[6]), .CK(clk_c), .Q(num_delay[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam num_delay_i6.GSR = "ENABLED";
    LUT4 i3_3_lut_3_lut_4_lut_4_lut (.A(char[0]), .B(n18378), .C(n17259), 
         .D(char[6]), .Z(n8_adj_95)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i3_3_lut_3_lut_4_lut_4_lut.init = 16'h1000;
    LUT4 i9018_2_lut_rep_221_3_lut (.A(cnt_init[4]), .B(cnt_init[3]), .C(cnt_init[2]), 
         .Z(n18394)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i9018_2_lut_rep_221_3_lut.init = 16'hfefe;
    LUT4 i9128_3_lut (.A(n1946), .B(n2324), .C(cnt_scan[0]), .Z(n17494)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9128_3_lut.init = 16'hcaca;
    LUT4 mux_369_Mux_1_i31_3_lut_4_lut (.A(n18017), .B(cnt[0]), .C(n18345), 
         .D(char_reg[1]), .Z(n3783)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;
    defparam mux_369_Mux_1_i31_3_lut_4_lut.init = 16'hf202;
    IB temp_p_pad_0 (.I(temp_p[0]), .O(temp_p_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(30[15:21])
    IB temp_p_pad_1 (.I(temp_p[1]), .O(temp_p_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(30[15:21])
    IB temp_p_pad_2 (.I(temp_p[2]), .O(temp_p_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(30[15:21])
    IB temp_p_pad_3 (.I(temp_p[3]), .O(temp_p_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(30[15:21])
    IB temp_l_pad_0 (.I(temp_l[0]), .O(temp_l_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(29[15:21])
    IB temp_l_pad_1 (.I(temp_l[1]), .O(temp_l_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(29[15:21])
    IB temp_l_pad_2 (.I(temp_l[2]), .O(temp_l_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(29[15:21])
    IB temp_l_pad_3 (.I(temp_l[3]), .O(temp_l_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(29[15:21])
    IB temp_h_pad_0 (.I(temp_h[0]), .O(temp_h_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(28[15:21])
    IB temp_h_pad_1 (.I(temp_h[1]), .O(temp_h_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(28[15:21])
    IB temp_h_pad_2 (.I(temp_h[2]), .O(temp_h_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(28[15:21])
    LUT4 mux_369_Mux_2_i31_3_lut_4_lut (.A(n18015), .B(cnt[0]), .C(n18345), 
         .D(char_reg[2]), .Z(n3782)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;
    defparam mux_369_Mux_2_i31_3_lut_4_lut.init = 16'hf202;
    IB temp_h_pad_3 (.I(temp_h[3]), .O(temp_h_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(28[15:21])
    IB min_l_pad_0 (.I(min_l[0]), .O(min_l_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(26[15:20])
    IB min_l_pad_1 (.I(min_l[1]), .O(min_l_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(26[15:20])
    IB min_l_pad_2 (.I(min_l[2]), .O(min_l_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(26[15:20])
    IB min_l_pad_3 (.I(min_l[3]), .O(min_l_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(26[15:20])
    IB min_h_pad_0 (.I(min_h[0]), .O(min_h_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(25[15:20])
    IB min_h_pad_1 (.I(min_h[1]), .O(min_h_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(25[15:20])
    IB min_h_pad_2 (.I(min_h[2]), .O(min_h_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(25[15:20])
    IB min_h_pad_3 (.I(min_h[3]), .O(min_h_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(25[15:20])
    LUT4 mux_369_Mux_7_i31_3_lut (.A(n18230), .B(char_reg[7]), .C(n18345), 
         .Z(n3777)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam mux_369_Mux_7_i31_3_lut.init = 16'hcaca;
    IB hour_l_pad_0 (.I(hour_l[0]), .O(hour_l_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(24[15:21])
    IB hour_l_pad_1 (.I(hour_l[1]), .O(hour_l_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(24[15:21])
    IB hour_l_pad_2 (.I(hour_l[2]), .O(hour_l_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(24[15:21])
    IB hour_l_pad_3 (.I(hour_l[3]), .O(hour_l_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(24[15:21])
    IB hour_h_pad_0 (.I(hour_h[0]), .O(hour_h_c_0));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(23[15:21])
    IB hour_h_pad_1 (.I(hour_h[1]), .O(hour_h_c_1));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(23[15:21])
    IB hour_h_pad_2 (.I(hour_h[2]), .O(hour_h_c_2));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(23[15:21])
    IB hour_h_pad_3 (.I(hour_h[3]), .O(hour_h_c_3));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(23[15:21])
    IB rst_n_pad (.I(rst_n), .O(rst_n_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(21[11:16])
    IB clk_pad (.I(clk), .O(clk_c));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(20[11:14])
    OB oled_dat_pad (.I(oled_dat_c), .O(oled_dat));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(36[15:23])
    LUT4 i3_4_lut_adj_22 (.A(cnt_main[0]), .B(cnt_main[2]), .C(n18413), 
         .D(n18349), .Z(n17220)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i3_4_lut_adj_22.init = 16'h0004;
    LUT4 i9483_then_4_lut (.A(num[4]), .B(n18377), .C(n2131), .D(n2130), 
         .Z(n18419)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i9483_then_4_lut.init = 16'h0004;
    LUT4 cnt_3__bdd_4_lut (.A(cnt[3]), .B(cnt[0]), .C(cnt[2]), .D(cnt[1]), 
         .Z(n18145)) /* synthesis lut_function=(!(A (B (C)+!B (C+!(D)))+!A (B+!(C (D)+!C !(D))))) */ ;
    defparam cnt_3__bdd_4_lut.init = 16'h1a09;
    OB oled_clk_pad (.I(oled_clk_c), .O(oled_clk));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(35[15:23])
    OB oled_dcn_pad (.I(oled_dcn_c), .O(oled_dcn));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(34[15:23])
    LUT4 i1_4_lut_adj_23 (.A(state[0]), .B(num_delay[3]), .C(n16_adj_21), 
         .D(n19_adj_42), .Z(num_delay_15__N_231[3])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_23.init = 16'hdc50;
    FD1P3IX cnt_delay_i0_i8 (.D(n2415), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[8]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i8.GSR = "ENABLED";
    LUT4 i5594_3_lut (.A(cnt_main[2]), .B(n18350), .C(cnt_main[0]), .Z(n9238)) /* synthesis lut_function=(!(A (B+!(C))+!A (B))) */ ;
    defparam i5594_3_lut.init = 16'h3131;
    LUT4 i2_3_lut_adj_24 (.A(n18345), .B(n67), .C(cnt_init[0]), .Z(n15910)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(98[7] 114[14])
    defparam i2_3_lut_adj_24.init = 16'h0202;
    FD1P3IX cnt_write_i0_i2 (.D(n2386), .SP(clk_c_enable_83), .CD(n11884), 
            .CK(clk_c), .Q(cnt_write[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_write_i0_i2.GSR = "ENABLED";
    LUT4 i20_4_lut_4_lut (.A(state[2]), .B(n4181), .C(n81), .D(state[3]), 
         .Z(n8_adj_2)) /* synthesis lut_function=(!(A ((D)+!C)+!A !(B (D)))) */ ;
    defparam i20_4_lut_4_lut.init = 16'h44a0;
    LUT4 n18360_bdd_3_lut_9877 (.A(n18360), .B(state[5]), .C(state[4]), 
         .Z(n18721)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam n18360_bdd_3_lut_9877.init = 16'h0202;
    FD1P3IX cnt_write_i0_i3 (.D(n2385), .SP(clk_c_enable_83), .CD(n11884), 
            .CK(clk_c), .Q(cnt_write[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_write_i0_i3.GSR = "ENABLED";
    CCU2D add_33_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15835), 
          .COUT(n15836), .S0(n283), .S1(n282));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_15.INIT0 = 16'h5aaa;
    defparam add_33_15.INIT1 = 16'h5aaa;
    defparam add_33_15.INJECT1_0 = "NO";
    defparam add_33_15.INJECT1_1 = "NO";
    LUT4 mux_369_Mux_6_i31_3_lut (.A(n18281), .B(char_reg[6]), .C(n18345), 
         .Z(n3778)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam mux_369_Mux_6_i31_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_25 (.A(state[1]), .B(n11_adj_70), .C(n92), .D(n18382), 
         .Z(state_5__N_596[1])) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A ((D)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i1_4_lut_adj_25.init = 16'h0ace;
    LUT4 i1_3_lut_adj_26 (.A(cnt_init[0]), .B(state[1]), .C(oled_dcn_N_650), 
         .Z(n11_adj_70)) /* synthesis lut_function=(A+(B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(98[7] 114[14])
    defparam i1_3_lut_adj_26.init = 16'heaea;
    LUT4 i2_3_lut_rep_204 (.A(n18396), .B(char[124]), .C(num[3]), .Z(n18377)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i2_3_lut_rep_204.init = 16'h8080;
    LUT4 i33_4_lut (.A(num_delay[3]), .B(num_delay_15__N_542[3]), .C(state[2]), 
         .D(n14000), .Z(n16_adj_21)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut.init = 16'h0aca;
    LUT4 i1251_2_lut_3_lut_4_lut (.A(n18411), .B(n18405), .C(state[1]), 
         .D(state[0]), .Z(n8230)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i1251_2_lut_3_lut_4_lut.init = 16'h0100;
    LUT4 i9262_2_lut (.A(state[3]), .B(state[5]), .Z(n17444)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i9262_2_lut.init = 16'heeee;
    LUT4 num_1426_mux_6_i1_4_lut (.A(state[0]), .B(n45_adj_34), .C(state[3]), 
         .D(n4_adj_91), .Z(n55)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_mux_6_i1_4_lut.init = 16'hc0c5;
    LUT4 n18414_bdd_4_lut_9872 (.A(n18414), .B(cnt_write[0]), .C(state[4]), 
         .D(oled_csn_N_634), .Z(n18723)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam n18414_bdd_4_lut_9872.init = 16'h4000;
    LUT4 i1_3_lut_rep_193_4_lut (.A(n18411), .B(n18405), .C(state[1]), 
         .D(state[0]), .Z(n18366)) /* synthesis lut_function=(!(A+(B+(C (D)+!C !(D))))) */ ;
    defparam i1_3_lut_rep_193_4_lut.init = 16'h0110;
    LUT4 i3484_2_lut (.A(clk_c_enable_84), .B(state[0]), .Z(n11842)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i3484_2_lut.init = 16'h8888;
    LUT4 cnt_0__bdd_3_lut_9552 (.A(cnt[0]), .B(cnt[2]), .C(cnt[1]), .Z(n18138)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C)+!B !(C)))) */ ;
    defparam cnt_0__bdd_3_lut_9552.init = 16'h1616;
    LUT4 i1_3_lut_rep_174_3_lut_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), 
         .C(oled_dcn_N_650), .D(n18402), .Z(n18347)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C+(D)))) */ ;
    defparam i1_3_lut_rep_174_3_lut_4_lut.init = 16'hff10;
    FD1P3IX cnt_delay_i0_i9 (.D(n2414), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[9]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i9.GSR = "ENABLED";
    LUT4 i1_2_lut_adj_27 (.A(state[3]), .B(n31_adj_76), .Z(n16110)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i1_2_lut_adj_27.init = 16'h4444;
    PFUMX i9660 (.BLUT(n18418), .ALUT(n18419), .C0(n2132), .Z(n18420));
    FD1P3IX cnt_delay_i0_i10 (.D(n2413), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[10]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i10.GSR = "ENABLED";
    PFUMX i1901 (.BLUT(n10247), .ALUT(n126), .C0(n18361), .Z(n10248));
    FD1P3IX cnt_delay_i0_i11 (.D(n2412), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[11]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i11.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i4 (.D(n2384), .SP(clk_c_enable_83), .CD(n11884), 
            .CK(clk_c), .Q(oled_csn_N_634));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_write_i0_i4.GSR = "ENABLED";
    FD1P3IX num_1426__i7 (.D(n38), .SP(clk_c_enable_72), .CD(n11870), 
            .CK(clk_c), .Q(num[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426__i7.GSR = "ENABLED";
    PFUMX i9639 (.BLUT(n18295), .ALUT(n18294), .C0(state[3]), .Z(n18296));
    FD1P3IX cnt_i0_i7 (.D(n315), .SP(clk_c_enable_73), .CD(n11894), .CK(clk_c), 
            .Q(cnt[7]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_i0_i7.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i14 (.D(n2409), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[14]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i14.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut (.A(state[2]), .B(n4181), .C(state_back[5]), .Z(n17217)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_2_lut_3_lut.init = 16'h4040;
    CCU2D add_33_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n15834), 
          .COUT(n15835), .S0(n285), .S1(n284));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam add_33_13.INIT0 = 16'h5aaa;
    defparam add_33_13.INIT1 = 16'h5aaa;
    defparam add_33_13.INJECT1_0 = "NO";
    defparam add_33_13.INJECT1_1 = "NO";
    LUT4 n18414_bdd_2_lut_9871 (.A(state[4]), .B(state_back[5]), .Z(n18722)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam n18414_bdd_2_lut_9871.init = 16'h4444;
    LUT4 i1_2_lut_3_lut_adj_28 (.A(state[2]), .B(n4181), .C(state_back[0]), 
         .Z(n17216)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_2_lut_3_lut_adj_28.init = 16'h4040;
    LUT4 i1_2_lut_3_lut_adj_29 (.A(state[2]), .B(n4181), .C(state_back[2]), 
         .Z(n17218)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_2_lut_3_lut_adj_29.init = 16'h4040;
    LUT4 i9662_then_4_lut (.A(cnt_main[1]), .B(cnt_main[4]), .C(cnt_main[3]), 
         .D(cnt_main[0]), .Z(n19020)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i9662_then_4_lut.init = 16'hfdff;
    FD1P3AX y_p_i0_i1 (.D(n16021), .SP(clk_c_enable_75), .CK(clk_c), .Q(y_p[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam y_p_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i0 (.D(cnt_main_4__N_298[0]), .SP(clk_c_enable_76), 
            .CD(n11846), .CK(clk_c), .Q(cnt_main[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_main_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i12 (.D(n2411), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[12]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i12.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i0 (.D(n2423), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_30 (.A(n16_adj_75), .B(n18411), .C(n18405), .D(n18073), 
         .Z(n16300)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_adj_30.init = 16'h3b0a;
    LUT4 i9662_else_4_lut (.A(cnt_main[1]), .B(cnt_main[4]), .C(cnt_main[3]), 
         .D(cnt_main[0]), .Z(n19019)) /* synthesis lut_function=(A (B+(C (D)+!C !(D)))+!A (B+(C+!(D)))) */ ;
    defparam i9662_else_4_lut.init = 16'hfcdf;
    FD1P3AX x_pl_i0_i3 (.D(n14127), .SP(clk_c_enable_79), .CK(clk_c), 
            .Q(x_pl[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam x_pl_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i1 (.D(n2422), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[1]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i2 (.D(n2421), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i2.GSR = "ENABLED";
    LUT4 i9281_2_lut_3_lut_4_lut_4_lut (.A(n18355), .B(n18393), .C(n18348), 
         .D(n14151), .Z(clk_c_enable_75)) /* synthesis lut_function=(!(A+((C (D))+!B))) */ ;
    defparam i9281_2_lut_3_lut_4_lut_4_lut.init = 16'h0444;
    FD1P3IX cnt_delay_i0_i3 (.D(n2420), .SP(clk_c_enable_82), .CD(n11852), 
            .CK(clk_c), .Q(cnt_delay[3]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_delay_i0_i3.GSR = "ENABLED";
    LUT4 cnt_3__bdd_4_lut_9541 (.A(cnt[3]), .B(cnt[2]), .C(cnt[0]), .D(cnt[1]), 
         .Z(n18137)) /* synthesis lut_function=(!(A (B (C)+!B (C+!(D)))+!A !(B (C+(D))))) */ ;
    defparam cnt_3__bdd_4_lut_9541.init = 16'h4e48;
    LUT4 i5684_2_lut (.A(n291), .B(oled_dcn_N_650), .Z(n317)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5684_2_lut.init = 16'h2222;
    LUT4 i5462_2_lut (.A(n296), .B(oled_dcn_N_650), .Z(n322)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5462_2_lut.init = 16'h2222;
    LUT4 i3530_2_lut (.A(clk_c_enable_59), .B(cnt_main[1]), .Z(n11888)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i3530_2_lut.init = 16'h2222;
    LUT4 i9240_2_lut (.A(clk_c_enable_72), .B(state[3]), .Z(n11870)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i9240_2_lut.init = 16'h2222;
    LUT4 i5683_2_lut (.A(n290), .B(oled_dcn_N_650), .Z(n316)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5683_2_lut.init = 16'h2222;
    PFUMX i9636 (.BLUT(n18291), .ALUT(n18290), .C0(cnt_scan[3]), .Z(n18292));
    LUT4 i3529_2_lut (.A(clk_c_enable_59), .B(cnt_main[1]), .Z(n11887)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i3529_2_lut.init = 16'h8888;
    LUT4 i33_4_lut_adj_31 (.A(num_delay[15]), .B(num_delay_15__N_542[15]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_44)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_31.init = 16'h0aca;
    LUT4 i2_3_lut_adj_32 (.A(cnt_main[4]), .B(cnt_main[1]), .C(n6_adj_88), 
         .Z(n7267)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i2_3_lut_adj_32.init = 16'h4040;
    LUT4 mux_369_Mux_0_i31_3_lut (.A(n18022), .B(char_reg[0]), .C(n18345), 
         .Z(n3784)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam mux_369_Mux_0_i31_3_lut.init = 16'hc5c5;
    LUT4 i17_3_lut (.A(cnt_main[2]), .B(cnt_main[3]), .C(cnt_main[0]), 
         .Z(n6_adj_88)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B))) */ ;
    defparam i17_3_lut.init = 16'h6464;
    LUT4 i1784_2_lut (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n2387)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(142[25:41])
    defparam i1784_2_lut.init = 16'h6666;
    LUT4 i1_4_lut_adj_33 (.A(n24_adj_54), .B(char_reg[4]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[4])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_33.init = 16'hce0a;
    FD1P3IX cnt_write_i0_i0 (.D(n4_adj_35), .SP(clk_c_enable_83), .CD(n11884), 
            .CK(clk_c), .Q(cnt_write[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam cnt_write_i0_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_adj_34 (.A(state[0]), .B(n5296), .Z(n34)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i1_2_lut_adj_34.init = 16'h8888;
    LUT4 i1_2_lut_rep_206_3_lut (.A(cnt_init[4]), .B(cnt_init[3]), .C(cnt_init[0]), 
         .Z(n18379)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_206_3_lut.init = 16'hfefe;
    LUT4 state_1__bdd_4_lut (.A(state[1]), .B(n9), .C(n30), .D(state[2]), 
         .Z(n18155)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam state_1__bdd_4_lut.init = 16'h0008;
    LUT4 i9250_2_lut (.A(state[4]), .B(state[5]), .Z(n17454)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i9250_2_lut.init = 16'heeee;
    LUT4 i33_4_lut_adj_35 (.A(num_delay[14]), .B(num_delay_15__N_542[14]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_43)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_35.init = 16'h0aca;
    CCU2D sub_1103_add_2_11 (.A0(cnt_delay[9]), .B0(num_delay[9]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[10]), .B1(num_delay[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15849), .COUT(n15850));
    defparam sub_1103_add_2_11.INIT0 = 16'h5999;
    defparam sub_1103_add_2_11.INIT1 = 16'h5999;
    defparam sub_1103_add_2_11.INJECT1_0 = "NO";
    defparam sub_1103_add_2_11.INJECT1_1 = "NO";
    LUT4 i5592_2_lut (.A(state[4]), .B(state_back[0]), .Z(n41_adj_83)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i5592_2_lut.init = 16'h1111;
    LUT4 i1_3_lut_4_lut_adj_36 (.A(n18400), .B(n18381), .C(n24_adj_39), 
         .D(n5296), .Z(clk_c_enable_5)) /* synthesis lut_function=(A (B (C (D)))+!A (C (D))) */ ;
    defparam i1_3_lut_4_lut_adj_36.init = 16'hd000;
    LUT4 i92_4_lut_adj_37 (.A(n15863), .B(n813), .C(cnt_scan[1]), .D(n17259), 
         .Z(n57_adj_10)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam i92_4_lut_adj_37.init = 16'hca0a;
    LUT4 i33_4_lut_adj_38 (.A(num_delay[13]), .B(num_delay_15__N_542[13]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_41)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_38.init = 16'h0aca;
    LUT4 i1_4_lut_adj_39 (.A(n18360), .B(num_delay[13]), .C(n16), .D(n18383), 
         .Z(num_delay_15__N_542[13])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_39.init = 16'hfefa;
    LUT4 state_5__I_0_318_i11_rep_78_2_lut_3_lut_4_lut (.A(state[3]), .B(n18411), 
         .C(n18399), .D(state[2]), .Z(n17670)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam state_5__I_0_318_i11_rep_78_2_lut_3_lut_4_lut.init = 16'hfeff;
    LUT4 i1805_3_lut_4_lut (.A(cnt_write[2]), .B(n18412), .C(cnt_write[3]), 
         .D(oled_csn_N_634), .Z(n2384)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(142[25:41])
    defparam i1805_3_lut_4_lut.init = 16'h7f80;
    LUT4 num_3__bdd_4_lut (.A(char[2]), .B(num[2]), .C(num[1]), .D(num[0]), 
         .Z(n17922)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam num_3__bdd_4_lut.init = 16'h0002;
    CCU2D sub_1103_add_2_9 (.A0(cnt_delay[7]), .B0(num_delay[7]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[8]), .B1(num_delay[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15848), .COUT(n15849));
    defparam sub_1103_add_2_9.INIT0 = 16'h5999;
    defparam sub_1103_add_2_9.INIT1 = 16'h5999;
    defparam sub_1103_add_2_9.INJECT1_0 = "NO";
    defparam sub_1103_add_2_9.INJECT1_1 = "NO";
    LUT4 i33_4_lut_adj_40 (.A(num_delay[12]), .B(num_delay_15__N_542[12]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_40)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_40.init = 16'h0aca;
    LUT4 i33_4_lut_adj_41 (.A(num_delay[11]), .B(num_delay_15__N_542[11]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_38)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_41.init = 16'h0aca;
    LUT4 num_3__bdd_4_lut_9378 (.A(char[122]), .B(num[2]), .C(num[1]), 
         .D(num[0]), .Z(n17921)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam num_3__bdd_4_lut_9378.init = 16'h8000;
    LUT4 i33_4_lut_adj_42 (.A(num_delay[10]), .B(num_delay_15__N_542[10]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_37)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_42.init = 16'h0aca;
    LUT4 i33_4_lut_adj_43 (.A(num_delay[9]), .B(num_delay_15__N_542[9]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_36)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_43.init = 16'h0aca;
    PFUMX i9630 (.BLUT(n18280), .ALUT(n18279), .C0(cnt[4]), .Z(n18281));
    LUT4 i33_4_lut_adj_44 (.A(num_delay[8]), .B(num_delay_15__N_542[8]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_26)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_44.init = 16'h0aca;
    LUT4 i1_4_lut_adj_45 (.A(n18360), .B(num_delay[8]), .C(n16_adj_17), 
         .D(n18383), .Z(num_delay_15__N_542[8])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_45.init = 16'hfefa;
    LUT4 i33_4_lut_adj_46 (.A(num_delay[7]), .B(num_delay_15__N_542[7]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_25)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_46.init = 16'h0aca;
    LUT4 i1_4_lut_adj_47 (.A(n18360), .B(num_delay[7]), .C(n16_adj_18), 
         .D(n18383), .Z(num_delay_15__N_542[7])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_47.init = 16'hfefa;
    LUT4 i33_4_lut_adj_48 (.A(num_delay[6]), .B(num_delay_15__N_542[6]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_48.init = 16'h0aca;
    LUT4 n1193_bdd_3_lut_9946 (.A(n1571), .B(n2327), .C(cnt_scan[1]), 
         .Z(n18910)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1193_bdd_3_lut_9946.init = 16'hcaca;
    CCU2D sub_1103_add_2_7 (.A0(cnt_delay[5]), .B0(num_delay[5]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[6]), .B1(num_delay[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15847), .COUT(n15848));
    defparam sub_1103_add_2_7.INIT0 = 16'h5999;
    defparam sub_1103_add_2_7.INIT1 = 16'h5999;
    defparam sub_1103_add_2_7.INJECT1_0 = "NO";
    defparam sub_1103_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_1103_add_2_5 (.A0(cnt_delay[3]), .B0(num_delay[3]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[4]), .B1(num_delay[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15846), .COUT(n15847));
    defparam sub_1103_add_2_5.INIT0 = 16'h5999;
    defparam sub_1103_add_2_5.INIT1 = 16'h5999;
    defparam sub_1103_add_2_5.INJECT1_0 = "NO";
    defparam sub_1103_add_2_5.INJECT1_1 = "NO";
    LUT4 i8989_3_lut (.A(state_back[1]), .B(n17267), .C(n18383), .Z(state_back_5__N_620[1])) /* synthesis lut_function=(A (B+(C))) */ ;
    defparam i8989_3_lut.init = 16'ha8a8;
    LUT4 n1193_bdd_3_lut (.A(n1193), .B(n1949), .C(cnt_scan[1]), .Z(n18911)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1193_bdd_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_49 (.A(cnt_init[0]), .B(n11507), .C(state_back[2]), 
         .D(n18402), .Z(n16_adj_71)) /* synthesis lut_function=(!(A+!(B+(C (D))))) */ ;
    defparam i1_4_lut_adj_49.init = 16'h5444;
    LUT4 n18912_bdd_2_lut (.A(n18912), .B(cnt_scan[2]), .Z(n18913)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n18912_bdd_2_lut.init = 16'h2222;
    LUT4 i2_3_lut_4_lut (.A(n18403), .B(n18386), .C(n14151), .D(n18354), 
         .Z(n16021)) /* synthesis lut_function=(!(A (C+(D))+!A ((C+(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(79[8:12])
    defparam i2_3_lut_4_lut.init = 16'h000e;
    LUT4 i8998_2_lut_rep_218 (.A(cnt_write[0]), .B(n18414), .C(oled_csn_N_634), 
         .Z(n18391)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;
    defparam i8998_2_lut_rep_218.init = 16'he0e0;
    LUT4 i6_4_lut (.A(n2130), .B(num[4]), .C(cnt_scan[0]), .D(n2132), 
         .Z(n14)) /* synthesis lut_function=(A+(B+!(C (D)))) */ ;
    defparam i6_4_lut.init = 16'hefff;
    LUT4 n815_bdd_4_lut (.A(n815), .B(x_pl[3]), .C(cnt_scan[2]), .D(cnt_scan[1]), 
         .Z(n18914)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B (C (D)))+!A !((C+(D))+!B)) */ ;
    defparam n815_bdd_4_lut.init = 16'ha00c;
    LUT4 n3446_bdd_2_lut_9981 (.A(n18914), .B(cnt_scan[0]), .Z(n18915)) /* synthesis lut_function=(A (B)) */ ;
    defparam n3446_bdd_2_lut_9981.init = 16'h8888;
    LUT4 cnt_1__bdd_3_lut (.A(cnt[1]), .B(cnt[2]), .C(cnt[0]), .Z(n18163)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A ((C)+!B))) */ ;
    defparam cnt_1__bdd_3_lut.init = 16'h2c2c;
    LUT4 i2_3_lut_rep_177_3_lut (.A(n18413), .B(n18354), .C(n7267), .Z(n18350)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i2_3_lut_rep_177_3_lut.init = 16'hfdfd;
    LUT4 i2761_2_lut (.A(n2130), .B(n2131), .Z(n11112)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[51:79])
    defparam i2761_2_lut.init = 16'heeee;
    PFUMX i9596 (.BLUT(n18229), .ALUT(n18228), .C0(cnt[0]), .Z(n18230));
    LUT4 i5637_2_lut_4_lut_4_lut (.A(n18413), .B(cnt_main[0]), .C(n18354), 
         .D(n7267), .Z(n9122)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i5637_2_lut_4_lut_4_lut.init = 16'h0008;
    LUT4 i1_4_lut_adj_50 (.A(n24_adj_50), .B(char_reg[3]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_50.init = 16'hce0a;
    LUT4 n9928_bdd_2_lut_9570_4_lut (.A(cnt_scan[4]), .B(n18417), .C(n14025), 
         .D(state[3]), .Z(n18173)) /* synthesis lut_function=(!(A+(B (C+!(D))+!B !(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[7] 138[14])
    defparam n9928_bdd_2_lut_9570_4_lut.init = 16'h1500;
    LUT4 i1_4_lut_adj_51 (.A(n24_adj_47), .B(char_reg[2]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_51.init = 16'hce0a;
    LUT4 n18175_bdd_2_lut (.A(n18339), .B(state[0]), .Z(n18176)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n18175_bdd_2_lut.init = 16'h2222;
    LUT4 cnt_0__bdd_3_lut_9629 (.A(cnt[0]), .B(cnt[1]), .C(cnt[2]), .Z(n18177)) /* synthesis lut_function=(A (B+!(C))+!A ((C)+!B)) */ ;
    defparam cnt_0__bdd_3_lut_9629.init = 16'hdbdb;
    LUT4 i5681_2_lut (.A(n289), .B(oled_dcn_N_650), .Z(n315)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5681_2_lut.init = 16'h2222;
    LUT4 i9297_2_lut_rep_171_3_lut_4_lut_4_lut_4_lut_4_lut (.A(state[0]), 
         .B(n18415), .C(n18389), .D(n18358), .Z(clk_c_enable_82)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (B ((D)+!C)+!B (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i9297_2_lut_rep_171_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h08fb;
    PFUMX i9310 (.BLUT(n17781), .ALUT(n17780), .C0(cnt_main[0]), .Z(n17782));
    LUT4 i2_3_lut_4_lut_adj_52 (.A(state[0]), .B(n18415), .C(n18411), 
         .D(state[3]), .Z(n11_adj_86)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i2_3_lut_4_lut_adj_52.init = 16'hfbff;
    LUT4 i5682_2_lut (.A(cnt_main[0]), .B(n18376), .Z(cnt_main_4__N_298[0])) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(73[12:40])
    defparam i5682_2_lut.init = 16'hdddd;
    LUT4 i2_3_lut_rep_181_4_lut (.A(state[2]), .B(n18389), .C(state[1]), 
         .D(state[0]), .Z(n18354)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(71[5:9])
    defparam i2_3_lut_rep_181_4_lut.init = 16'hffef;
    LUT4 i9189_3_lut_then_3_lut (.A(n2329), .B(n1951), .C(cnt_scan[0]), 
         .Z(n18426)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam i9189_3_lut_then_3_lut.init = 16'hacac;
    LUT4 i9260_2_lut_rep_170_3_lut_4_lut_4_lut_4_lut_4_lut (.A(state[0]), 
         .B(n18415), .C(n18389), .D(n18356), .Z(clk_c_enable_83)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (B ((D)+!C)+!B (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i9260_2_lut_rep_170_3_lut_4_lut_4_lut_4_lut_4_lut.init = 16'h08fb;
    LUT4 equal_1007_i11_2_lut_rep_198_3_lut_4_lut (.A(state[0]), .B(n18415), 
         .C(n18411), .D(state[3]), .Z(n18371)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam equal_1007_i11_2_lut_rep_198_3_lut_4_lut.init = 16'hfffb;
    LUT4 i1_2_lut_4_lut_adj_53 (.A(n18145), .B(n3781), .C(n18342), .D(state[2]), 
         .Z(n6_adj_51)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_53.init = 16'hac00;
    LUT4 i1878_1_lut (.A(cnt_write[0]), .Z(n4_adj_35)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(143[7] 163[14])
    defparam i1878_1_lut.init = 16'h5555;
    LUT4 i1_4_lut_adj_54 (.A(cnt_main[1]), .B(n38_adj_28), .C(x_ph[4]), 
         .D(n19018), .Z(n11)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C))) */ ;
    defparam i1_4_lut_adj_54.init = 16'hcfcd;
    LUT4 i1_4_lut_adj_55 (.A(n18296), .B(char_reg[1]), .C(n18381), .D(n27), 
         .Z(char_reg_7__N_203[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_55.init = 16'hce0a;
    LUT4 i9293_2_lut (.A(cnt_scan[3]), .B(cnt_scan[1]), .Z(n17435)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i9293_2_lut.init = 16'hbbbb;
    LUT4 n18173_bdd_4_lut (.A(n18173), .B(n18172), .C(state[2]), .D(state[1]), 
         .Z(n18339)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n18173_bdd_4_lut.init = 16'h00ca;
    LUT4 i1_2_lut_4_lut_adj_56 (.A(n22), .B(n3782), .C(n17438), .D(state[2]), 
         .Z(n6_adj_48)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_56.init = 16'hac00;
    LUT4 i3528_3_lut_4_lut_4_lut (.A(n18370), .B(n18356), .C(n18391), 
         .D(n18371), .Z(n11884)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (D)+!B (C (D))))) */ ;
    defparam i3528_3_lut_4_lut_4_lut.init = 16'h7400;
    LUT4 i1_2_lut_3_lut_4_lut_adj_57 (.A(state[0]), .B(n18415), .C(n18411), 
         .D(state[3]), .Z(n4)) /* synthesis lut_function=(A (C+(D))+!A (B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i1_2_lut_3_lut_4_lut_adj_57.init = 16'hfff4;
    LUT4 i9483_else_4_lut (.A(num[4]), .B(n18377), .C(n2131), .D(n2130), 
         .Z(n18418)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i9483_else_4_lut.init = 16'h1000;
    LUT4 i3488_2_lut_3_lut_3_lut_4_lut (.A(state[0]), .B(n18415), .C(n18354), 
         .D(n18355), .Z(n11846)) /* synthesis lut_function=(!(A ((D)+!C)+!A (B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i3488_2_lut_3_lut_3_lut_4_lut.init = 16'h00b0;
    LUT4 i1733_3_lut_4_lut (.A(cnt_init[2]), .B(n18416), .C(cnt_init[3]), 
         .D(cnt_init[4]), .Z(n245)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(99[49:64])
    defparam i1733_3_lut_4_lut.init = 16'h7f80;
    LUT4 i1_3_lut_adj_58 (.A(state[1]), .B(state[2]), .C(state[0]), .Z(n17281)) /* synthesis lut_function=(A+(B (C))) */ ;
    defparam i1_3_lut_adj_58.init = 16'heaea;
    PFUMX i9303 (.BLUT(n17769), .ALUT(n17764), .C0(n7267), .Z(char_167__N_358[2]));
    LUT4 i50_4_lut_4_lut (.A(state[1]), .B(state[2]), .C(n17354), .D(n9), 
         .Z(n28_adj_73)) /* synthesis lut_function=(!(A (B+(D))+!A !(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i50_4_lut_4_lut.init = 16'h4062;
    LUT4 i2_3_lut_4_lut_adj_59 (.A(n18354), .B(n7267), .C(cnt_main[0]), 
         .D(n18413), .Z(n11759)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i2_3_lut_4_lut_adj_59.init = 16'h1000;
    LUT4 i1697_3_lut_4_lut (.A(cnt_main[2]), .B(n18406), .C(cnt_main[3]), 
         .D(cnt_main[4]), .Z(n7)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(73[24:39])
    defparam i1697_3_lut_4_lut.init = 16'h7f80;
    LUT4 i1_4_lut_adj_60 (.A(state[0]), .B(n18355), .C(n16_adj_77), .D(x_ph[4]), 
         .Z(x_ph_7__N_11[4])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_60.init = 16'hdc50;
    LUT4 i2_4_lut_adj_61 (.A(cnt_init[0]), .B(n4_adj_87), .C(num_delay[3]), 
         .D(n18347), .Z(num_delay_15__N_542[3])) /* synthesis lut_function=(A (B)+!A (B+(C (D)))) */ ;
    defparam i2_4_lut_adj_61.init = 16'hdccc;
    LUT4 i1_3_lut_rep_182_4_lut (.A(state[2]), .B(n18389), .C(state[0]), 
         .D(state[1]), .Z(n18355)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(71[5:9])
    defparam i1_3_lut_rep_182_4_lut.init = 16'hfeee;
    LUT4 i3511_2_lut_3_lut_4_lut_4_lut (.A(n18370), .B(n18358), .C(n2405), 
         .D(n18371), .Z(n11852)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (D)+!B (C (D))))) */ ;
    defparam i3511_2_lut_3_lut_4_lut_4_lut.init = 16'h7400;
    LUT4 n18001_bdd_2_lut_4_lut (.A(n18138), .B(n3783), .C(n17438), .D(state[2]), 
         .Z(n18295)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam n18001_bdd_2_lut_4_lut.init = 16'hac00;
    LUT4 i9246_3_lut_3_lut (.A(n18354), .B(n14151), .C(n9_adj_27), .Z(n14161)) /* synthesis lut_function=(!(A+(B (C)))) */ ;
    defparam i9246_3_lut_3_lut.init = 16'h1515;
    CCU2D sub_1103_add_2_3 (.A0(cnt_delay[1]), .B0(num_delay[1]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[2]), .B1(num_delay[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n15845), .COUT(n15846));
    defparam sub_1103_add_2_3.INIT0 = 16'h5999;
    defparam sub_1103_add_2_3.INIT1 = 16'h5999;
    defparam sub_1103_add_2_3.INJECT1_0 = "NO";
    defparam sub_1103_add_2_3.INJECT1_1 = "NO";
    LUT4 i2_4_lut_rep_178 (.A(n18371), .B(n18253), .C(n18370), .D(n18354), 
         .Z(clk_c_enable_59)) /* synthesis lut_function=(!((B (C+!(D))+!B (C (D)))+!A)) */ ;
    defparam i2_4_lut_rep_178.init = 16'h0a22;
    LUT4 i1_2_lut_4_lut_4_lut_adj_62 (.A(n2132), .B(num[4]), .C(n18363), 
         .D(n11112), .Z(n17256)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i1_2_lut_4_lut_4_lut_adj_62.init = 16'h0020;
    LUT4 i1_2_lut_rep_180 (.A(n2130), .B(num[4]), .Z(n18353)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[51:79])
    defparam i1_2_lut_rep_180.init = 16'h2222;
    LUT4 i5468_2_lut_rep_222 (.A(cnt_init[4]), .B(cnt_init[3]), .Z(n18395)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5468_2_lut_rep_222.init = 16'heeee;
    CCU2D sub_1103_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[0]), .B1(num_delay[0]), .C1(GND_net), 
          .D1(GND_net), .COUT(n15845));
    defparam sub_1103_add_2_1.INIT0 = 16'h0000;
    defparam sub_1103_add_2_1.INIT1 = 16'h5999;
    defparam sub_1103_add_2_1.INJECT1_0 = "NO";
    defparam sub_1103_add_2_1.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_63 (.A(state[0]), .B(num_delay[4]), .C(n16_adj_22), 
         .D(n19_adj_42), .Z(num_delay_15__N_231[4])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_63.init = 16'hdc50;
    CCU2D num_1426_add_4_9 (.A0(cnt_scan[3]), .B0(n11418), .C0(num[7]), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15856), .S0(n38));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam num_1426_add_4_9.INIT0 = 16'he1e1;
    defparam num_1426_add_4_9.INIT1 = 16'h0000;
    defparam num_1426_add_4_9.INJECT1_0 = "NO";
    defparam num_1426_add_4_9.INJECT1_1 = "NO";
    LUT4 i9189_3_lut_else_3_lut (.A(n1195), .B(n1573), .C(cnt_scan[0]), 
         .Z(n18425)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9189_3_lut_else_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_3_lut_4_lut_adj_64 (.A(cnt_init[4]), .B(cnt_init[3]), 
         .C(cnt_init[1]), .D(cnt_init[0]), .Z(n71)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_64.init = 16'hfffe;
    LUT4 i33_4_lut_adj_65 (.A(x_ph[4]), .B(n18385), .C(state[1]), .D(n17197), 
         .Z(n16_adj_77)) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A (B+((D)+!C)))) */ ;
    defparam i33_4_lut_adj_65.init = 16'h0a3a;
    LUT4 cnt_scan_2__bdd_4_lut_9905 (.A(cnt_scan[2]), .B(cnt_scan[3]), .C(cnt_scan[0]), 
         .D(cnt_scan[1]), .Z(n18204)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B+!(C (D))))) */ ;
    defparam cnt_scan_2__bdd_4_lut_9905.init = 16'h1008;
    LUT4 n9928_bdd_3_lut_9569_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), .C(state[3]), 
         .D(n17872), .Z(n18172)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam n9928_bdd_3_lut_9569_4_lut.init = 16'h0100;
    PFUMX i9399 (.BLUT(n17961), .ALUT(n17960), .C0(cnt[1]), .Z(n17962));
    LUT4 cnt_0__bdd_4_lut_9438 (.A(cnt[0]), .B(cnt[3]), .C(cnt[2]), .D(cnt[4]), 
         .Z(n17961)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B (C)+!B (D)))) */ ;
    defparam cnt_0__bdd_4_lut_9438.init = 16'h041d;
    LUT4 n3446_bdd_2_lut_9598_3_lut (.A(n2130), .B(num[4]), .C(n18220), 
         .Z(n18221)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[51:79])
    defparam n3446_bdd_2_lut_9598_3_lut.init = 16'h2020;
    LUT4 i1_3_lut_rep_210_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), .C(cnt_init[0]), 
         .D(cnt_init[2]), .Z(n18383)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;
    defparam i1_3_lut_rep_210_4_lut.init = 16'hfeee;
    LUT4 cnt_0__bdd_3_lut_9445 (.A(cnt[3]), .B(cnt[2]), .C(cnt[4]), .Z(n17960)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
    defparam cnt_0__bdd_3_lut_9445.init = 16'h0404;
    CCU2D add_107_17 (.A0(cnt_delay[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n15844), .S0(n2408));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(168[29:45])
    defparam add_107_17.INIT0 = 16'h5aaa;
    defparam add_107_17.INIT1 = 16'h0000;
    defparam add_107_17.INJECT1_0 = "NO";
    defparam add_107_17.INJECT1_1 = "NO";
    LUT4 i5734_2_lut_rep_196_3_lut_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), 
         .C(cnt_init[0]), .D(n18402), .Z(n18369)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5734_2_lut_rep_196_3_lut_4_lut.init = 16'hfffe;
    LUT4 n647_bdd_4_lut_9498_4_lut (.A(n2130), .B(num[4]), .C(n18377), 
         .D(n2132), .Z(n18078)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[51:79])
    defparam n647_bdd_4_lut_9498_4_lut.init = 16'h0002;
    FD1P3IX state_i0_i5 (.D(n18726), .SP(clk_c_enable_84), .CD(n14137), 
            .CK(clk_c), .Q(state[5]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam state_i0_i5.GSR = "ENABLED";
    LUT4 i1_rep_48_2_lut (.A(cnt_main[2]), .B(cnt_main[4]), .Z(n19018)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(90[8:13])
    defparam i1_rep_48_2_lut.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_adj_66 (.A(cnt_init[4]), .B(cnt_init[3]), 
         .C(cnt_init[2]), .D(cnt_init[0]), .Z(n92)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_66.init = 16'hfffe;
    LUT4 i2_3_lut_rep_223 (.A(num[2]), .B(num[1]), .C(num[0]), .Z(n18396)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i2_3_lut_rep_223.init = 16'h8080;
    LUT4 hour_h_c_3_bdd_2_lut_9374 (.A(hour_h_c_3), .B(cnt_main[2]), .Z(n17781)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam hour_h_c_3_bdd_2_lut_9374.init = 16'h2222;
    LUT4 i5643_2_lut_4_lut (.A(num[2]), .B(num[1]), .C(num[0]), .D(char[123]), 
         .Z(n1866)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5643_2_lut_4_lut.init = 16'h8000;
    LUT4 i5678_3_lut_rep_224 (.A(char[5]), .B(num[4]), .Z(n18397)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5678_3_lut_rep_224.init = 16'h2222;
    LUT4 i9291_2_lut_2_lut_4_lut (.A(n18385), .B(state[0]), .C(state[1]), 
         .D(n14097), .Z(n14127)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(71[5:9])
    defparam i9291_2_lut_2_lut_4_lut.init = 16'h0010;
    LUT4 n18292_bdd_3_lut_4_lut (.A(n4181), .B(char_reg[1]), .C(cnt_scan[4]), 
         .D(n18292), .Z(n18293)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A !(C+!(D))) */ ;
    defparam n18292_bdd_3_lut_4_lut.init = 16'h8f80;
    PFUMX i91 (.BLUT(n45), .ALUT(n57_adj_15), .C0(n17435), .Z(n63_adj_11));
    LUT4 i2_2_lut_3_lut (.A(char[5]), .B(num[4]), .C(n11401), .Z(n7_adj_96)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i2_2_lut_3_lut.init = 16'h2020;
    LUT4 i9000_2_lut_rep_176_4_lut (.A(n18385), .B(state[0]), .C(state[1]), 
         .D(n7267), .Z(n18349)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(71[5:9])
    defparam i9000_2_lut_rep_176_4_lut.init = 16'hffef;
    LUT4 i1_4_lut_adj_67 (.A(state[4]), .B(state[0]), .C(n18414), .D(n18391), 
         .Z(n34_adj_84)) /* synthesis lut_function=(!((B (C+!(D))+!B (C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_adj_67.init = 16'h0a22;
    LUT4 i9002_2_lut_3_lut (.A(char[5]), .B(num[4]), .C(n2131), .Z(n17366)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i9002_2_lut_3_lut.init = 16'h2020;
    LUT4 i1261_2_lut_rep_225 (.A(cnt_scan[0]), .B(cnt_scan[1]), .Z(n18398)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[7] 138[14])
    defparam i1261_2_lut_rep_225.init = 16'h8888;
    LUT4 i1764_2_lut_3_lut_4_lut (.A(cnt_scan[0]), .B(cnt_scan[1]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n10105)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[7] 138[14])
    defparam i1764_2_lut_3_lut_4_lut.init = 16'h8000;
    LUT4 i9056_3_lut (.A(n18345), .B(cnt[4]), .C(cnt[3]), .Z(n17422)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam i9056_3_lut.init = 16'h1010;
    LUT4 cnt_4__bdd_4_lut_9716 (.A(cnt[4]), .B(cnt[2]), .C(cnt[3]), .D(cnt[1]), 
         .Z(n18229)) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A !(B+!(D)))) */ ;
    defparam cnt_4__bdd_4_lut_9716.init = 16'h4e7f;
    LUT4 i1_2_lut_adj_68 (.A(cnt_scan[4]), .B(n63), .Z(n64)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_68.init = 16'h4444;
    LUT4 cnt_4__bdd_2_lut_9889 (.A(cnt[4]), .B(cnt[2]), .Z(n18228)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam cnt_4__bdd_2_lut_9889.init = 16'h4444;
    LUT4 i1755_2_lut_3_lut (.A(cnt_scan[0]), .B(cnt_scan[1]), .C(cnt_scan[2]), 
         .Z(n457)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[7] 138[14])
    defparam i1755_2_lut_3_lut.init = 16'h7878;
    LUT4 i1762_2_lut_3_lut_4_lut (.A(cnt_scan[0]), .B(cnt_scan[1]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n456)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[7] 138[14])
    defparam i1762_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i5483_2_lut_rep_226 (.A(state[1]), .B(state[0]), .Z(n18399)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5483_2_lut_rep_226.init = 16'heeee;
    LUT4 i9072_3_lut (.A(n18345), .B(cnt[4]), .C(cnt[3]), .Z(n17438)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam i9072_3_lut.init = 16'h0404;
    LUT4 i1_2_lut_rep_192_3_lut_4_lut (.A(state[1]), .B(state[0]), .C(n18400), 
         .D(n18411), .Z(n18365)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i1_2_lut_rep_192_3_lut_4_lut.init = 16'h0010;
    LUT4 i1_2_lut_rep_207_3_lut (.A(state[1]), .B(state[0]), .C(state[2]), 
         .Z(n18380)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i1_2_lut_rep_207_3_lut.init = 16'hefef;
    LUT4 i5793_2_lut_3_lut (.A(state[1]), .B(state[0]), .C(clk_c_enable_84), 
         .Z(n14137)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;
    defparam i5793_2_lut_3_lut.init = 16'he0e0;
    LUT4 i24_2_lut_rep_227 (.A(state[2]), .B(state[3]), .Z(n18400)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i24_2_lut_rep_227.init = 16'h6666;
    LUT4 i1_2_lut_adj_69 (.A(cnt_scan[4]), .B(n63_adj_11), .Z(n64_adj_12)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_69.init = 16'h4444;
    LUT4 n18252_bdd_2_lut (.A(n18252), .B(cnt_main[4]), .Z(n18253)) /* synthesis lut_function=(A+(B)) */ ;
    defparam n18252_bdd_2_lut.init = 16'heeee;
    LUT4 i2_3_lut_4_lut_4_lut_adj_70 (.A(state[2]), .B(state[3]), .C(cnt_scan[4]), 
         .D(n18381), .Z(n17272)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i2_3_lut_4_lut_4_lut_adj_70.init = 16'h0004;
    LUT4 i5639_2_lut_rep_228 (.A(state[2]), .B(state[0]), .Z(n18401)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5639_2_lut_rep_228.init = 16'heeee;
    LUT4 cnt_main_4__bdd_4_lut (.A(cnt_main[0]), .B(cnt_main[3]), .C(cnt_main[2]), 
         .D(cnt_main[1]), .Z(n18252)) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B !(C+(D)))) */ ;
    defparam cnt_main_4__bdd_4_lut.init = 16'hc0c1;
    LUT4 i1_2_lut_adj_71 (.A(cnt_scan[4]), .B(n18115), .Z(n64_adj_16)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_71.init = 16'h4444;
    LUT4 i9040_3_lut_4_lut (.A(state[2]), .B(state[0]), .C(n18375), .D(state[5]), 
         .Z(n10_adj_1)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i9040_3_lut_4_lut.init = 16'h0001;
    LUT4 hour_h_c_3_bdd_3_lut_9375 (.A(temp_h_c_3), .B(hour_l_c_3), .C(cnt_main[2]), 
         .Z(n17780)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam hour_h_c_3_bdd_3_lut_9375.init = 16'hacac;
    PFUMX i9949 (.BLUT(n18915), .ALUT(n18913), .C0(cnt_scan[3]), .Z(n18916));
    LUT4 i1_4_lut_4_lut_adj_72 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_24), 
         .D(num_delay[6]), .Z(num_delay_15__N_231[6])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_72.init = 16'hdc50;
    LUT4 i1_2_lut_rep_229 (.A(cnt_init[2]), .B(cnt_init[1]), .Z(n18402)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_2_lut_rep_229.init = 16'hdddd;
    LUT4 i5633_2_lut_rep_209_3_lut_4_lut (.A(cnt_init[2]), .B(cnt_init[1]), 
         .C(cnt_init[3]), .D(cnt_init[4]), .Z(n18382)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i5633_2_lut_rep_209_3_lut_4_lut.init = 16'hfffd;
    LUT4 n8010_bdd_2_lut_4_lut (.A(hour_h_c_1), .B(hour_l_c_1), .C(cnt_main[0]), 
         .D(n18413), .Z(n17761)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n8010_bdd_2_lut_4_lut.init = 16'h00ca;
    LUT4 n8011_bdd_2_lut_4_lut (.A(hour_h_c_0), .B(hour_l_c_0), .C(cnt_main[0]), 
         .D(n18413), .Z(n17787)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n8011_bdd_2_lut_4_lut.init = 16'h00ca;
    LUT4 equal_14_i6_2_lut_rep_230 (.A(cnt_main[0]), .B(cnt_main[1]), .Z(n18403)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(84[8:12])
    defparam equal_14_i6_2_lut_rep_230.init = 16'hbbbb;
    PFUMX i9947 (.BLUT(n18911), .ALUT(n18910), .C0(cnt_scan[0]), .Z(n18912));
    LUT4 i1_2_lut_rep_175_4_lut (.A(n18385), .B(state[0]), .C(state[1]), 
         .D(n9_adj_27), .Z(n18348)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(71[5:9])
    defparam i1_2_lut_rep_175_4_lut.init = 16'h1000;
    LUT4 equal_10_i9_2_lut_rep_194_3_lut_4_lut (.A(cnt_main[0]), .B(cnt_main[1]), 
         .C(n19018), .D(cnt_main[3]), .Z(n18367)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(84[8:12])
    defparam equal_10_i9_2_lut_rep_194_3_lut_4_lut.init = 16'hfffb;
    LUT4 i1_2_lut_adj_73 (.A(cnt_scan[4]), .B(n18916), .Z(n64_adj_74)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_73.init = 16'h4444;
    LUT4 equal_12_i6_2_lut_rep_231 (.A(cnt_main[0]), .B(cnt_main[1]), .Z(n18404)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(81[8:12])
    defparam equal_12_i6_2_lut_rep_231.init = 16'heeee;
    LUT4 equal_8_i9_2_lut_3_lut_4_lut (.A(cnt_main[0]), .B(cnt_main[1]), 
         .C(n19018), .D(cnt_main[3]), .Z(n9)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(81[8:12])
    defparam equal_8_i9_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i5464_2_lut_rep_232 (.A(state[3]), .B(state[2]), .Z(n18405)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5464_2_lut_rep_232.init = 16'heeee;
    LUT4 i5495_4_lut (.A(n18221), .B(n18397), .C(n17256), .D(n18362), 
         .Z(n126)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[51:79])
    defparam i5495_4_lut.init = 16'hc088;
    LUT4 i9013_3_lut_4_lut (.A(state[3]), .B(state[2]), .C(state[4]), 
         .D(state[0]), .Z(n17378)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9013_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_4_lut_4_lut_adj_74 (.A(cnt_main[3]), .B(cnt_main[0]), .C(cnt_main[2]), 
         .D(cnt_main[4]), .Z(n38_adj_28)) /* synthesis lut_function=(!(A (C+(D))+!A (B (D)+!B ((D)+!C)))) */ ;
    defparam i1_4_lut_4_lut_adj_74.init = 16'h005e;
    LUT4 i1_2_lut_adj_75 (.A(state[3]), .B(state[2]), .Z(n24_adj_31)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_75.init = 16'h8888;
    LUT4 i1_4_lut_4_lut_adj_76 (.A(oled_csn_N_634), .B(n18390), .C(state[4]), 
         .D(n5296), .Z(n17266)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;
    defparam i1_4_lut_4_lut_adj_76.init = 16'h6000;
    LUT4 i1662_2_lut_rep_233 (.A(cnt_main[0]), .B(cnt_main[1]), .Z(n18406)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1662_2_lut_rep_233.init = 16'h8888;
    LUT4 cnt_0__bdd_3_lut_9883 (.A(cnt[0]), .B(cnt[1]), .C(cnt[2]), .Z(n18280)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam cnt_0__bdd_3_lut_9883.init = 16'h4040;
    LUT4 cnt_0__bdd_4_lut_9882 (.A(cnt[0]), .B(cnt[3]), .C(cnt[1]), .D(cnt[2]), 
         .Z(n18279)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B+(C (D))))) */ ;
    defparam cnt_0__bdd_4_lut_9882.init = 16'h0311;
    LUT4 i5763_4_lut (.A(n18363), .B(n14), .C(n17366), .D(n18377), .Z(n10247)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i5763_4_lut.init = 16'h0010;
    LUT4 i1_2_lut_adj_77 (.A(cnt_scan[4]), .B(n63_adj_6), .Z(n64_adj_7)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_77.init = 16'h4444;
    LUT4 i1_2_lut_4_lut_adj_78 (.A(n18137), .B(n3784), .C(n18342), .D(state[2]), 
         .Z(n6_adj_46)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_78.init = 16'hac00;
    LUT4 n18001_bdd_3_lut (.A(n18001), .B(n4181), .C(char_reg[1]), .Z(n18291)) /* synthesis lut_function=(A+(B (C))) */ ;
    defparam n18001_bdd_3_lut.init = 16'heaea;
    LUT4 i1_2_lut_adj_79 (.A(cnt_scan[4]), .B(n18128), .Z(n64_adj_3)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_79.init = 16'h4444;
    LUT4 n818_bdd_3_lut_9759 (.A(n818), .B(cnt_scan[2]), .C(cnt_scan[1]), 
         .Z(n17991)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n818_bdd_3_lut_9759.init = 16'h8080;
    LUT4 i1690_2_lut_3_lut_4_lut (.A(cnt_main[0]), .B(cnt_main[1]), .C(cnt_main[3]), 
         .D(cnt_main[2]), .Z(n8)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;
    defparam i1690_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 n818_bdd_4_lut (.A(y_p[0]), .B(cnt_scan[2]), .C(x_ph[0]), .D(cnt_scan[1]), 
         .Z(n17992)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam n818_bdd_4_lut.init = 16'h3022;
    LUT4 i9238_4_lut_rep_240 (.A(cnt_main[4]), .B(cnt_main[1]), .C(cnt_main[2]), 
         .D(cnt_main[3]), .Z(n18413)) /* synthesis lut_function=(A+(B+(C (D)+!C !(D)))) */ ;
    defparam i9238_4_lut_rep_240.init = 16'hfeef;
    LUT4 i1_4_lut_4_lut_adj_80 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_38), 
         .D(num_delay[11]), .Z(num_delay_15__N_231[11])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_80.init = 16'hdc50;
    LUT4 n7097_bdd_3_lut_9335 (.A(temp_l_c_3), .B(cnt_main[0]), .C(cnt_main[2]), 
         .Z(n17779)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam n7097_bdd_3_lut_9335.init = 16'h2020;
    LUT4 cnt_main_3__bdd_4_lut (.A(cnt_main[3]), .B(n18410), .C(cnt_main[1]), 
         .D(n19018), .Z(n14151)) /* synthesis lut_function=(A (B)+!A (B ((D)+!C))) */ ;
    defparam cnt_main_3__bdd_4_lut.init = 16'hcc8c;
    LUT4 i1_4_lut_4_lut_adj_81 (.A(cnt_main[0]), .B(cnt_main[1]), .C(n18387), 
         .D(n18410), .Z(n17304)) /* synthesis lut_function=(A (B+(C (D)))+!A (B (D)+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(82[2] 83[12])
    defparam i1_4_lut_4_lut_adj_81.init = 16'hfc98;
    LUT4 i9268_4_lut (.A(state[0]), .B(num_delay[2]), .C(n24_adj_20), 
         .D(n19_adj_42), .Z(num_delay_15__N_231[2])) /* synthesis lut_function=(A (B+!(D))+!A !(B (C)+!B (C+(D)))) */ ;
    defparam i9268_4_lut.init = 16'h8caf;
    LUT4 n7267_bdd_3_lut_9314 (.A(n8013), .B(min_h_c_3), .C(cnt_main[0]), 
         .Z(n17778)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n7267_bdd_3_lut_9314.init = 16'hacac;
    LUT4 i2_2_lut_4_lut (.A(cnt_scan[4]), .B(n14025), .C(n18417), .D(n11418), 
         .Z(n6)) /* synthesis lut_function=(A (D)+!A (B ((D)+!C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(136[8:13])
    defparam i2_2_lut_4_lut.init = 16'hff04;
    LUT4 i1_4_lut_4_lut_adj_82 (.A(cnt_main[0]), .B(n17270), .C(n11), 
         .D(n18386), .Z(n17197)) /* synthesis lut_function=(A (B (C (D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(82[2] 83[12])
    defparam i1_4_lut_4_lut_adj_82.init = 16'hc040;
    LUT4 i1_2_lut_rep_213_3_lut (.A(cnt_main[2]), .B(cnt_main[4]), .C(cnt_main[3]), 
         .Z(n18386)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(90[8:13])
    defparam i1_2_lut_rep_213_3_lut.init = 16'hfefe;
    LUT4 i1_4_lut_4_lut_adj_83 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_41), 
         .D(num_delay[13]), .Z(num_delay_15__N_231[13])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_83.init = 16'hdc50;
    LUT4 i42_4_lut_3_lut (.A(state[0]), .B(state_5__N_596[1]), .C(state[2]), 
         .Z(n28)) /* synthesis lut_function=(!(A (C)+!A !(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i42_4_lut_3_lut.init = 16'h4a4a;
    LUT4 shift_right_67_i2132_4_lut (.A(char[3]), .B(n1866), .C(num[3]), 
         .D(n11097), .Z(n2132)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam shift_right_67_i2132_4_lut.init = 16'hcac0;
    PFUMX i91_adj_84 (.BLUT(n57_adj_10), .ALUT(n61_adj_8), .C0(cnt_scan[3]), 
          .Z(n63_adj_6));
    LUT4 i2_3_lut_rep_241 (.A(cnt_write[2]), .B(cnt_write[3]), .C(cnt_write[1]), 
         .Z(n18414)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(143[7] 163[14])
    defparam i2_3_lut_rep_241.init = 16'hfefe;
    LUT4 i1_4_lut_4_lut_adj_85 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_44), 
         .D(num_delay[15]), .Z(num_delay_15__N_231[15])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_85.init = 16'hdc50;
    LUT4 i5718_2_lut_rep_217_4_lut (.A(cnt_write[2]), .B(cnt_write[3]), 
         .C(cnt_write[1]), .D(cnt_write[0]), .Z(n18390)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(143[7] 163[14])
    defparam i5718_2_lut_rep_217_4_lut.init = 16'hfffe;
    LUT4 i9288_2_lut_rep_242 (.A(state[1]), .B(state[2]), .Z(n18415)) /* synthesis lut_function=(!(A+(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i9288_2_lut_rep_242.init = 16'h1111;
    LUT4 state_1__bdd_2_lut_3_lut (.A(state[1]), .B(state[2]), .C(state_back[3]), 
         .Z(n18154)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam state_1__bdd_2_lut_3_lut.init = 16'h1010;
    LUT4 i48_4_lut_4_lut (.A(state[1]), .B(state[2]), .C(state[4]), .D(state_back[2]), 
         .Z(n33)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i48_4_lut_4_lut.init = 16'h0100;
    LUT4 i41_4_lut (.A(num_delay[2]), .B(n14000), .C(state[2]), .D(n17209), 
         .Z(n24_adj_20)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C)))) */ ;
    defparam i41_4_lut.init = 16'h3505;
    LUT4 i1_2_lut_rep_200_3_lut_4_lut (.A(state[1]), .B(state[2]), .C(state[3]), 
         .D(state[0]), .Z(n18373)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i1_2_lut_rep_200_3_lut_4_lut.init = 16'hfffe;
    LUT4 state_5__I_0_i8_2_lut_rep_220_3_lut (.A(state[1]), .B(state[2]), 
         .C(state[0]), .Z(n18393)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam state_5__I_0_i8_2_lut_rep_220_3_lut.init = 16'hfefe;
    PFUMX i9379 (.BLUT(n17922), .ALUT(n17921), .C0(num[3]), .Z(n2131));
    LUT4 i9277_2_lut_rep_168_2_lut_4_lut_4_lut_4_lut (.A(state[1]), .B(state[2]), 
         .C(n18385), .D(state[0]), .Z(clk_c_enable_76)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C)+!B (C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i9277_2_lut_rep_168_2_lut_4_lut_4_lut_4_lut.init = 16'h050e;
    LUT4 cnt_4__bdd_4_lut_9539 (.A(cnt[3]), .B(cnt[2]), .C(cnt[0]), .D(cnt[1]), 
         .Z(n17995)) /* synthesis lut_function=(!(A+!(B (C (D)+!C !(D))+!B !(C (D))))) */ ;
    defparam cnt_4__bdd_4_lut_9539.init = 16'h4115;
    LUT4 shift_right_67_i2130_4_lut (.A(char[1]), .B(n1866), .C(num[3]), 
         .D(n11097), .Z(n2130)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam shift_right_67_i2130_4_lut.init = 16'hcac0;
    LUT4 cnt_4__bdd_3_lut (.A(cnt[2]), .B(cnt[0]), .C(cnt[1]), .Z(n17996)) /* synthesis lut_function=(!(A (B)+!A (B+!(C)))) */ ;
    defparam cnt_4__bdd_3_lut.init = 16'h3232;
    LUT4 i1_4_lut_adj_86 (.A(state[0]), .B(n18355), .C(n16_adj_79), .D(x_ph[2]), 
         .Z(x_ph_7__N_11[2])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_86.init = 16'hdc50;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    LUT4 i33_4_lut_adj_87 (.A(x_ph[2]), .B(x_ph_7__N_326[2]), .C(state[1]), 
         .D(n18385), .Z(n16_adj_79)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_87.init = 16'h0aca;
    LUT4 i1676_2_lut (.A(cnt_main[1]), .B(cnt_main[0]), .Z(n10)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(73[24:39])
    defparam i1676_2_lut.init = 16'h6666;
    LUT4 i1_3_lut_adj_88 (.A(n13907), .B(x_ph[2]), .C(n9_adj_27), .Z(x_ph_7__N_326[2])) /* synthesis lut_function=((B (C))+!A) */ ;
    defparam i1_3_lut_adj_88.init = 16'hd5d5;
    LUT4 i1_4_lut_adj_89 (.A(cnt_main[4]), .B(n18404), .C(cnt_main[2]), 
         .D(cnt_main[3]), .Z(n9_adj_27)) /* synthesis lut_function=(A+(B (C (D))+!B (C (D)+!C !(D)))) */ ;
    defparam i1_4_lut_adj_89.init = 16'hfaab;
    LUT4 i1_3_lut_3_lut (.A(state[2]), .B(n4181), .C(state_back[3]), .Z(n12_adj_58)) /* synthesis lut_function=(!(A+!((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_3_lut_3_lut.init = 16'h5151;
    LUT4 i1_2_lut_rep_214_3_lut (.A(cnt_main[2]), .B(cnt_main[4]), .C(cnt_main[3]), 
         .Z(n18387)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(90[8:13])
    defparam i1_2_lut_rep_214_3_lut.init = 16'hefef;
    PFUMX i67 (.BLUT(n17266), .ALUT(n34), .C0(n18366), .Z(n39));
    LUT4 i1_4_lut_4_lut_adj_90 (.A(state[2]), .B(n4181), .C(n64_adj_12), 
         .D(char_reg[4]), .Z(n12_adj_56)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_90.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_91 (.A(state[2]), .B(n4181), .C(n18009), .D(char_reg[0]), 
         .Z(n12)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_91.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_92 (.A(state[2]), .B(n4181), .C(n64_adj_7), 
         .D(char_reg[5]), .Z(n12_adj_63)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_92.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_93 (.A(state[2]), .B(n4181), .C(n64), .D(char_reg[7]), 
         .Z(n12_adj_69)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_93.init = 16'h5450;
    LUT4 i1_4_lut_adj_94 (.A(state[0]), .B(n18355), .C(n16_adj_80), .D(x_ph[1]), 
         .Z(x_ph_7__N_11[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_94.init = 16'hdc50;
    LUT4 i33_4_lut_adj_95 (.A(x_ph[1]), .B(x_ph_7__N_326[1]), .C(state[1]), 
         .D(n18385), .Z(n16_adj_80)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_95.init = 16'h0aca;
    LUT4 i2_4_lut_adj_96 (.A(n17307), .B(n17304), .C(x_ph[1]), .D(n9_adj_27), 
         .Z(x_ph_7__N_326[1])) /* synthesis lut_function=(((C (D))+!B)+!A) */ ;
    defparam i2_4_lut_adj_96.init = 16'hf777;
    LUT4 i1_4_lut_4_lut_adj_97 (.A(state[2]), .B(n4181), .C(n64_adj_3), 
         .D(char_reg[6]), .Z(n12_adj_66)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_97.init = 16'h5450;
    LUT4 n17782_bdd_3_lut (.A(n17782), .B(n17779), .C(n18413), .Z(n17783)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17782_bdd_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_4_lut_adj_98 (.A(state[2]), .B(n4181), .C(n64_adj_74), 
         .D(char_reg[3]), .Z(n12_adj_52)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_98.init = 16'h5450;
    LUT4 n3446_bdd_2_lut_9641_2_lut (.A(state[2]), .B(n18293), .Z(n18294)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam n3446_bdd_2_lut_9641_2_lut.init = 16'h4444;
    LUT4 i1_2_lut_4_lut_adj_99 (.A(n18177), .B(n3777), .C(n17422), .D(state[2]), 
         .Z(n6_adj_68)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_99.init = 16'hac00;
    LUT4 oled_dcn_N_650_bdd_3_lut_3_lut (.A(state[2]), .B(n18375), .C(n18392), 
         .Z(n18070)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam oled_dcn_N_650_bdd_3_lut_3_lut.init = 16'h0404;
    LUT4 i1_4_lut_4_lut_adj_100 (.A(state[2]), .B(n4181), .C(n64_adj_16), 
         .D(char_reg[2]), .Z(n12_adj_49)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_100.init = 16'h5450;
    PFUMX i9548 (.BLUT(n18155), .ALUT(n18154), .C0(state[5]), .Z(n18156));
    LUT4 i33_4_lut_adj_101 (.A(num_delay[4]), .B(num_delay_15__N_542[4]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_22)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_101.init = 16'h0aca;
    LUT4 n817_bdd_3_lut_9466 (.A(n817), .B(cnt_scan[2]), .C(cnt_scan[1]), 
         .Z(n17999)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n817_bdd_3_lut_9466.init = 16'h8080;
    LUT4 i1_4_lut_4_lut_adj_102 (.A(state[2]), .B(n18365), .C(n16826), 
         .D(n18392), .Z(n4_adj_53)) /* synthesis lut_function=(A (C)+!A !(B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_102.init = 16'hb0f0;
    LUT4 i1_4_lut_4_lut_adj_103 (.A(cnt_init[0]), .B(n17353), .C(n19_adj_13), 
         .D(state[2]), .Z(n6_adj_60)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_103.init = 16'hf400;
    LUT4 n817_bdd_4_lut_9467 (.A(y_p[1]), .B(cnt_scan[2]), .C(x_ph[1]), 
         .D(cnt_scan[1]), .Z(n18000)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam n817_bdd_4_lut_9467.init = 16'h3022;
    LUT4 i1_4_lut_4_lut_adj_104 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[15]), .Z(num_delay_15__N_542[15])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_104.init = 16'hdc00;
    LUT4 i1_3_lut_3_lut_adj_105 (.A(cnt_init[0]), .B(n18347), .C(num_delay[13]), 
         .Z(n16)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_3_lut_3_lut_adj_105.init = 16'h4040;
    LUT4 i1_4_lut_4_lut_adj_106 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[10]), .Z(num_delay_15__N_542[10])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_106.init = 16'hdc00;
    LUT4 i1_4_lut_4_lut_adj_107 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[11]), .Z(num_delay_15__N_542[11])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_107.init = 16'hdc00;
    LUT4 i1_4_lut_4_lut_adj_108 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[12]), .Z(num_delay_15__N_542[12])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_108.init = 16'hdc00;
    LUT4 i1_3_lut_3_lut_adj_109 (.A(cnt_init[0]), .B(n18347), .C(num_delay[8]), 
         .Z(n16_adj_17)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_3_lut_3_lut_adj_109.init = 16'h4040;
    LUT4 i1_4_lut_4_lut_adj_110 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[6]), .Z(num_delay_15__N_542[6])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_110.init = 16'hdc00;
    LUT4 i1_4_lut_4_lut_adj_111 (.A(cnt_init[0]), .B(n18383), .C(n18347), 
         .D(num_delay[9]), .Z(num_delay_15__N_542[9])) /* synthesis lut_function=(A (B (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_111.init = 16'hdc00;
    LUT4 i1_4_lut_adj_112 (.A(cnt_init[0]), .B(num_delay[4]), .C(n18347), 
         .D(n18383), .Z(num_delay_15__N_542[4])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_112.init = 16'hcc40;
    PFUMX i9826 (.BLUT(n18723), .ALUT(n18722), .C0(state[5]), .Z(n18724));
    LUT4 i2_4_lut_4_lut (.A(cnt_init[0]), .B(n18347), .C(num_delay[14]), 
         .D(n4_adj_94), .Z(num_delay_15__N_542[14])) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i2_4_lut_4_lut.init = 16'hff40;
    LUT4 i1_4_lut_4_lut_adj_113 (.A(cnt_init[0]), .B(n17313), .C(n19_adj_78), 
         .D(state[2]), .Z(n6_adj_30)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_113.init = 16'hf400;
    LUT4 i1_3_lut_3_lut_adj_114 (.A(cnt_init[0]), .B(n18347), .C(num_delay[7]), 
         .Z(n16_adj_18)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_3_lut_3_lut_adj_114.init = 16'h4040;
    LUT4 i2_3_lut_4_lut_4_lut_adj_115 (.A(cnt_init[0]), .B(state[2]), .C(cnt_init[2]), 
         .D(n18395), .Z(n17275)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i2_3_lut_4_lut_4_lut_adj_115.init = 16'h0004;
    LUT4 i1714_2_lut_rep_243 (.A(cnt_init[1]), .B(cnt_init[0]), .Z(n18416)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(99[49:64])
    defparam i1714_2_lut_rep_243.init = 16'h8888;
    LUT4 n17466_bdd_3_lut_9511 (.A(n1196), .B(n1574), .C(cnt_scan[0]), 
         .Z(n18004)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17466_bdd_3_lut_9511.init = 16'hcaca;
    LUT4 i1_4_lut_adj_116 (.A(cnt_init[0]), .B(num_delay[2]), .C(n15), 
         .D(n18383), .Z(n17209)) /* synthesis lut_function=(!(A (B (D))+!A (B (C+(D))+!B (C)))) */ ;
    defparam i1_4_lut_adj_116.init = 16'h23af;
    LUT4 i2_3_lut_rep_237 (.A(cnt_main[3]), .B(cnt_main[4]), .C(cnt_main[2]), 
         .Z(n18410)) /* synthesis lut_function=(A+(B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(80[8:12])
    defparam i2_3_lut_rep_237.init = 16'hefef;
    LUT4 n18078_bdd_2_lut (.A(n18078), .B(n647), .Z(n18079)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n18078_bdd_2_lut.init = 16'h2222;
    LUT4 i1719_2_lut_3_lut (.A(cnt_init[1]), .B(cnt_init[0]), .C(cnt_init[2]), 
         .Z(n247)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(99[49:64])
    defparam i1719_2_lut_3_lut.init = 16'h7878;
    LUT4 i1726_2_lut_3_lut_4_lut (.A(cnt_init[1]), .B(cnt_init[0]), .C(cnt_init[3]), 
         .D(cnt_init[2]), .Z(n246)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(99[49:64])
    defparam i1726_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i5487_2_lut_rep_244 (.A(cnt_scan[0]), .B(cnt_scan[1]), .Z(n18417)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5487_2_lut_rep_244.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_3_lut (.A(cnt_main[3]), .B(cnt_main[4]), .C(cnt_main[2]), 
         .Z(n17270)) /* synthesis lut_function=(A (B+(C))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(80[8:12])
    defparam i1_2_lut_3_lut_4_lut_3_lut.init = 16'heded;
    LUT4 i1_3_lut_rep_219_4_lut (.A(cnt_scan[0]), .B(cnt_scan[1]), .C(n14025), 
         .D(cnt_scan[4]), .Z(n18392)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;
    defparam i1_3_lut_rep_219_4_lut.init = 16'hffe0;
    LUT4 i2_3_lut_rep_202_4_lut (.A(cnt_scan[0]), .B(cnt_scan[1]), .C(n14025), 
         .D(cnt_scan[4]), .Z(n18375)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
    defparam i2_3_lut_rep_202_4_lut.init = 16'hffef;
    PFUMX i9530 (.BLUT(n18127), .ALUT(n18126), .C0(cnt_scan[3]), .Z(n18128));
    LUT4 i2_3_lut_rep_183_4_lut (.A(state[3]), .B(n18393), .C(state[5]), 
         .D(state[4]), .Z(n18356)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i2_3_lut_rep_183_4_lut.init = 16'hfeff;
    LUT4 n17991_bdd_3_lut_9968 (.A(n17991), .B(n17992), .C(cnt_scan[0]), 
         .Z(n18007)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n17991_bdd_3_lut_9968.init = 16'hacac;
    LUT4 mux_369_Mux_2_i22_4_lut_3_lut (.A(cnt[1]), .B(cnt[2]), .C(cnt[0]), 
         .Z(n22)) /* synthesis lut_function=(A (B)+!A !(B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[20] 110[14])
    defparam mux_369_Mux_2_i22_4_lut_3_lut.init = 16'h9898;
    LUT4 n18008_bdd_2_lut (.A(n18008), .B(cnt_scan[4]), .Z(n18009)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n18008_bdd_2_lut.init = 16'h2222;
    LUT4 cnt_0__bdd_4_lut_9446 (.A(cnt[4]), .B(cnt[3]), .C(cnt[1]), .D(cnt[2]), 
         .Z(n18017)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C (D))+!B !(C (D)+!C !(D))))) */ ;
    defparam cnt_0__bdd_4_lut_9446.init = 16'h144f;
    LUT4 i5531_2_lut_rep_238 (.A(state[5]), .B(state[4]), .Z(n18411)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i5531_2_lut_rep_238.init = 16'heeee;
    LUT4 i1_2_lut_rep_216_3_lut (.A(state[5]), .B(state[4]), .C(state[3]), 
         .Z(n18389)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_216_3_lut.init = 16'hfefe;
    LUT4 cnt_1__bdd_4_lut_9442 (.A(cnt[1]), .B(cnt[4]), .C(cnt[3]), .D(cnt[2]), 
         .Z(n18015)) /* synthesis lut_function=(!(A (B+!(C+(D)))+!A (D))) */ ;
    defparam cnt_1__bdd_4_lut_9442.init = 16'h2275;
    LUT4 i1_4_lut_adj_117 (.A(state[0]), .B(num_delay[1]), .C(n16_adj_19), 
         .D(n19_adj_42), .Z(num_delay_15__N_231[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_117.init = 16'hdc50;
    LUT4 i1_4_lut_adj_118 (.A(cnt_init[0]), .B(n18402), .C(n18395), .D(oled_dcn_N_650), 
         .Z(n17267)) /* synthesis lut_function=(!(A+!(B+!(C+!(D))))) */ ;
    defparam i1_4_lut_adj_118.init = 16'h4544;
    LUT4 i33_4_lut_adj_119 (.A(num_delay[1]), .B(num_delay_15__N_542[1]), 
         .C(state[2]), .D(n14000), .Z(n16_adj_19)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_119.init = 16'h0aca;
    LUT4 i9080_2_lut_rep_169_4_lut (.A(n18402), .B(oled_dcn_N_650), .C(n18379), 
         .D(cnt[4]), .Z(n18342)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam i9080_2_lut_rep_169_4_lut.init = 16'h0001;
    LUT4 n7267_bdd_3_lut (.A(cnt_main[0]), .B(n8016), .C(min_h_c_0), .Z(n17785)) /* synthesis lut_function=(A (B)+!A (C)) */ ;
    defparam n7267_bdd_3_lut.init = 16'hd8d8;
    LUT4 i1_4_lut_adj_120 (.A(state[0]), .B(n18355), .C(n16_adj_81), .D(x_ph[0]), 
         .Z(x_ph_7__N_11[0])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_120.init = 16'hdc50;
    LUT4 i33_4_lut_adj_121 (.A(x_ph[0]), .B(x_ph_7__N_326[0]), .C(state[1]), 
         .D(n18385), .Z(n16_adj_81)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_121.init = 16'h0aca;
    PFUMX i9092 (.BLUT(n17456), .ALUT(n17457), .C0(cnt_scan[1]), .Z(n17458));
    LUT4 i1_3_lut_adj_122 (.A(n17307), .B(x_ph[0]), .C(n9_adj_27), .Z(x_ph_7__N_326[0])) /* synthesis lut_function=((B (C))+!A) */ ;
    defparam i1_3_lut_adj_122.init = 16'hd5d5;
    LUT4 i1_4_lut_adj_123 (.A(cnt_init[0]), .B(num_delay[1]), .C(n18347), 
         .D(n18383), .Z(num_delay_15__N_542[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_123.init = 16'hcc40;
    LUT4 equal_1013_i9_2_lut_rep_197_3_lut_3_lut_4_lut (.A(state[5]), .B(state[4]), 
         .C(state[3]), .D(n18415), .Z(n18370)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam equal_1013_i9_2_lut_rep_197_3_lut_3_lut_4_lut.init = 16'hfeff;
    LUT4 i9265_2_lut_4_lut_4_lut (.A(n18367), .B(state[1]), .C(state[0]), 
         .D(n18385), .Z(n13963)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i9265_2_lut_4_lut_4_lut.init = 16'h0004;
    LUT4 i1_4_lut_adj_124 (.A(n24_adj_45), .B(char_reg[0]), .C(n18381), 
         .D(n27), .Z(char_reg_7__N_203[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_124.init = 16'hce0a;
    LUT4 cnt_1__bdd_4_lut_9540 (.A(cnt[1]), .B(cnt[3]), .C(cnt[0]), .D(cnt[2]), 
         .Z(n18022)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B (C+(D))+!B (C (D)))) */ ;
    defparam cnt_1__bdd_4_lut_9540.init = 16'hfcea;
    LUT4 n17762_bdd_3_lut (.A(n17762), .B(n17759), .C(n7267), .Z(char_167__N_358[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17762_bdd_3_lut.init = 16'hcaca;
    LUT4 i9249_4_lut (.A(n50), .B(n17546), .C(n18405), .D(n18399), .Z(n42_adj_82)) /* synthesis lut_function=(A (B (C+(D)))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i9249_4_lut.init = 16'hccc4;
    LUT4 i9248_4_lut (.A(n44_adj_85), .B(n18411), .C(n18176), .D(n18405), 
         .Z(n17546)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i9248_4_lut.init = 16'hcfcd;
    LUT4 i72_4_lut (.A(state[0]), .B(n30), .C(state[1]), .D(n9), .Z(n44_adj_85)) /* synthesis lut_function=(!(A (C)+!A (B ((D)+!C)+!B !(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i72_4_lut.init = 16'h1a5a;
    LUT4 i2_3_lut_rep_185_4_lut (.A(state[3]), .B(n18393), .C(state[5]), 
         .D(state[4]), .Z(n18358)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(165[5:10])
    defparam i2_3_lut_rep_185_4_lut.init = 16'hffef;
    LUT4 i1_3_lut_adj_125 (.A(cnt_main[4]), .B(cnt_main[3]), .C(cnt_main[2]), 
         .Z(n30)) /* synthesis lut_function=(A+(B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam i1_3_lut_adj_125.init = 16'heaea;
    LUT4 i2_3_lut_4_lut_adj_126 (.A(state[5]), .B(state[4]), .C(state[2]), 
         .D(n39_adj_90), .Z(clk_c_enable_72)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i2_3_lut_4_lut_adj_126.init = 16'h0100;
    LUT4 i34_4_lut (.A(state[4]), .B(state[0]), .C(n18366), .D(n17213), 
         .Z(n24_adj_39)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;
    defparam i34_4_lut.init = 16'hcac0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_127 (.A(state[5]), .B(state[4]), .C(n17281), 
         .D(state[3]), .Z(n19_adj_42)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_127.init = 16'hfffe;
    LUT4 i9122_3_lut (.A(char_reg[3]), .B(char_reg[2]), .C(cnt_write[1]), 
         .Z(n17488)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i9122_3_lut.init = 16'hcaca;
    LUT4 i3_4_lut_adj_128 (.A(cnt_write[3]), .B(n17528), .C(cnt_write[2]), 
         .D(cnt_write[1]), .Z(n17213)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i3_4_lut_adj_128.init = 16'h0001;
    LUT4 n7267_bdd_3_lut_9308 (.A(n8014), .B(min_h_c_2), .C(cnt_main[0]), 
         .Z(n17764)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n7267_bdd_3_lut_9308.init = 16'hacac;
    LUT4 i1_4_lut_4_lut_adj_129 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_36), 
         .D(num_delay[9]), .Z(num_delay_15__N_231[9])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_129.init = 16'hdc50;
    PFUMX i56 (.BLUT(n33_adj_92), .ALUT(n37), .C0(state[1]), .Z(n39_adj_90));
    LUT4 i1_4_lut_4_lut_adj_130 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_43), 
         .D(num_delay[14]), .Z(num_delay_15__N_231[14])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_130.init = 16'hdc50;
    PFUMX i9528 (.BLUT(n18124), .ALUT(n17494), .C0(cnt_scan[1]), .Z(n18125));
    LUT4 i9230_2_lut (.A(oled_csn_N_634), .B(cnt_write[0]), .Z(n17528)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i9230_2_lut.init = 16'h6666;
    LUT4 i5544_2_lut_rep_208_3_lut_4_lut (.A(state[5]), .B(state[4]), .C(state[0]), 
         .D(state[1]), .Z(n18381)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5544_2_lut_rep_208_3_lut_4_lut.init = 16'hfffe;
    LUT4 n18076_bdd_3_lut (.A(n18420), .B(n11401), .C(cnt_scan[0]), .Z(n18077)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n18076_bdd_3_lut.init = 16'hcaca;
    PFUMX i10010 (.BLUT(n19019), .ALUT(n19020), .C0(cnt_main[2]), .Z(n17307));
    LUT4 i11_4_lut (.A(state[4]), .B(state[0]), .C(n18366), .D(oled_csn_N_634), 
         .Z(n16974)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i11_4_lut.init = 16'hcac0;
    LUT4 i2_3_lut_4_lut_adj_131 (.A(state[5]), .B(state[4]), .C(state[1]), 
         .D(state[3]), .Z(n14000)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2_3_lut_4_lut_adj_131.init = 16'hfffe;
    LUT4 i1639_4_lut_rep_203 (.A(n18406), .B(cnt_main[4]), .C(cnt_main[3]), 
         .D(cnt_main[2]), .Z(n18376)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1639_4_lut_rep_203.init = 16'hfcec;
    LUT4 n8011_bdd_4_lut (.A(cnt_main[0]), .B(n18413), .C(temp_h_c_0), 
         .D(temp_l_c_0), .Z(n17786)) /* synthesis lut_function=(!(A (B+!(C))+!A !((D)+!B))) */ ;
    defparam n8011_bdd_4_lut.init = 16'h7531;
    PFUMX i9518 (.BLUT(n18114), .ALUT(n18112), .C0(cnt_scan[3]), .Z(n18115));
    LUT4 n1947_bdd_3_lut_9453 (.A(n1947), .B(n2325), .C(cnt_scan[0]), 
         .Z(n18034)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1947_bdd_3_lut_9453.init = 16'hcaca;
    PFUMX i9301 (.BLUT(n17767), .ALUT(n17766), .C0(cnt_main[0]), .Z(n17768));
    LUT4 n1947_bdd_3_lut (.A(n1191), .B(n1569), .C(cnt_scan[0]), .Z(n18035)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1947_bdd_3_lut.init = 16'hcaca;
    PFUMX i9514 (.BLUT(n18110), .ALUT(n18037), .C0(cnt_scan[1]), .Z(n18111));
    LUT4 i1_4_lut_adj_132 (.A(n19), .B(cnt[4]), .C(n20), .D(n4_adj_93), 
         .Z(oled_dcn_N_650)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_132.init = 16'hfefa;
    LUT4 i8_4_lut (.A(cnt[5]), .B(cnt[11]), .C(cnt[10]), .D(cnt[13]), 
         .Z(n19)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i9_4_lut (.A(cnt[9]), .B(n18), .C(cnt[8]), .D(cnt[6]), .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i7_4_lut (.A(cnt[7]), .B(cnt[14]), .C(cnt[12]), .D(cnt[15]), 
         .Z(n18)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i7_4_lut.init = 16'hfffe;
    LUT4 i1_3_lut_adj_133 (.A(state[2]), .B(state_back[3]), .C(n81), .Z(n6_adj_57)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_3_lut_adj_133.init = 16'h8080;
    LUT4 i1_4_lut_adj_134 (.A(state[1]), .B(n17378), .C(state[5]), .D(n47), 
         .Z(n5296)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C+!(D))+!B !(C+(D))))) */ ;
    defparam i1_4_lut_adj_134.init = 16'h1712;
    LUT4 n1950_bdd_3_lut_9456 (.A(n1950), .B(n2328), .C(cnt_scan[0]), 
         .Z(n18037)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1950_bdd_3_lut_9456.init = 16'hcaca;
    LUT4 i5549_2_lut_rep_212_3_lut_4_lut (.A(state[5]), .B(state[4]), .C(state[2]), 
         .D(state[3]), .Z(n18385)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5549_2_lut_rep_212_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_4_lut_adj_135 (.A(n24_adj_59), .B(state_back[5]), .C(n18381), 
         .D(n27), .Z(state_back_5__N_285[5])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_135.init = 16'hce0a;
    LUT4 i2_4_lut_adj_136 (.A(n17281), .B(n18401), .C(n18411), .D(state[3]), 
         .Z(n27)) /* synthesis lut_function=(A+(B (C+(D))+!B (C+!(D)))) */ ;
    defparam i2_4_lut_adj_136.init = 16'hfefb;
    LUT4 i1_4_lut_4_lut_adj_137 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_26), 
         .D(num_delay[8]), .Z(num_delay_15__N_231[8])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_137.init = 16'hdc50;
    LUT4 i5617_3_lut_4_lut (.A(n18406), .B(cnt_main[4]), .C(cnt_main[3]), 
         .D(cnt_main[2]), .Z(cnt_main_4__N_298[2])) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B+(D))) */ ;
    defparam i5617_3_lut_4_lut.init = 16'hfdee;
    LUT4 i1_4_lut_adj_138 (.A(n24_adj_29), .B(state_back[0]), .C(n18381), 
         .D(n27), .Z(state_back_5__N_285[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_138.init = 16'hce0a;
    LUT4 i1_2_lut_3_lut_4_lut_adj_139 (.A(cnt[1]), .B(cnt[2]), .C(cnt[3]), 
         .D(cnt[0]), .Z(n4_adj_93)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_139.init = 16'hf0e0;
    LUT4 i9270_4_lut (.A(state[0]), .B(num_delay[0]), .C(n14147), .D(n19_adj_42), 
         .Z(num_delay_15__N_231[0])) /* synthesis lut_function=(A (B+!(D))+!A (B (C)+!B !((D)+!C))) */ ;
    defparam i9270_4_lut.init = 16'hc8fa;
    LUT4 i41_4_lut_adj_140 (.A(num_delay[0]), .B(n18383), .C(state[2]), 
         .D(n4_adj_89), .Z(n14147)) /* synthesis lut_function=(A (B+((D)+!C))+!A (C (D))) */ ;
    defparam i41_4_lut_adj_140.init = 16'hfa8a;
    LUT4 i1_4_lut_4_lut_adj_141 (.A(state[0]), .B(n19_adj_42), .C(n16_adj_37), 
         .D(num_delay[10]), .Z(num_delay_15__N_231[10])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i1_4_lut_4_lut_adj_141.init = 16'hdc50;
    LUT4 i1_3_lut_adj_142 (.A(n14000), .B(cnt_init[0]), .C(n15_adj_5), 
         .Z(n4_adj_89)) /* synthesis lut_function=(A+!(B+!(C))) */ ;
    defparam i1_3_lut_adj_142.init = 16'hbaba;
    LUT4 i1_3_lut_adj_143 (.A(n18346), .B(n67), .C(n18345), .Z(clk_c_enable_55)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;
    defparam i1_3_lut_adj_143.init = 16'h5454;
    LUT4 i1712_2_lut (.A(cnt_init[1]), .B(cnt_init[0]), .Z(n248)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(99[49:64])
    defparam i1712_2_lut.init = 16'h6666;
    LUT4 i1_4_lut_adj_144 (.A(n17670), .B(cnt_init[2]), .C(n18395), .D(cnt_init[1]), 
         .Z(n11202)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(97[5:9])
    defparam i1_4_lut_adj_144.init = 16'h5450;
    LUT4 i5737_4_lut (.A(n11_adj_86), .B(n18340), .C(n6), .D(cnt_scan[3]), 
         .Z(clk_c_enable_84)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i5737_4_lut.init = 16'hccc8;
    VLO i1 (.Z(GND_net));
    LUT4 mux_369_Mux_3_i30_4_lut_3_lut_4_lut (.A(cnt[1]), .B(cnt[2]), .C(cnt[3]), 
         .D(cnt[0]), .Z(n14143)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (C (D)))) */ ;
    defparam mux_369_Mux_3_i30_4_lut_3_lut_4_lut.init = 16'hfee0;
    LUT4 i1_4_lut_adj_145 (.A(n17670), .B(n18395), .C(n71), .D(cnt_init[2]), 
         .Z(n67)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_145.init = 16'hfaee;
    LUT4 n17788_bdd_3_lut (.A(n17788), .B(n17785), .C(n7267), .Z(char_167__N_358[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n17788_bdd_3_lut.init = 16'hcaca;
    LUT4 i2_3_lut_adj_146 (.A(n23), .B(state[1]), .C(state[4]), .Z(n16098)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam i2_3_lut_adj_146.init = 16'h0202;
    LUT4 i9295_4_lut_4_lut (.A(num[4]), .B(n11112), .C(n2132), .D(n18362), 
         .Z(n11401)) /* synthesis lut_function=(A (D)+!A !(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(74[7] 95[14])
    defparam i9295_4_lut_4_lut.init = 16'hab00;
    LUT4 i1_2_lut_3_lut_adj_147 (.A(cnt_scan[2]), .B(cnt_scan[0]), .C(y_p[4]), 
         .Z(n15863)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i1_2_lut_3_lut_adj_147.init = 16'h1010;
    LUT4 i1_2_lut_4_lut_adj_148 (.A(cnt_scan[4]), .B(n14025), .C(n18417), 
         .D(n9_adj_4), .Z(n4_adj_9)) /* synthesis lut_function=(A (D)+!A (B (C (D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(136[8:13])
    defparam i1_2_lut_4_lut_adj_148.init = 16'hfb00;
    LUT4 i2_4_lut_adj_149 (.A(cnt_scan[4]), .B(n4_adj_9), .C(n11_adj_86), 
         .D(n10105), .Z(n17200)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A ((C+!(D))+!B))) */ ;
    defparam i2_4_lut_adj_149.init = 16'h0408;
    LUT4 oled_dcn_N_650_bdd_4_lut_9684 (.A(oled_dcn_N_650), .B(n18369), 
         .C(n92), .D(state[4]), .Z(n18071)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(D))+!A (B (C+!(D))))) */ ;
    defparam oled_dcn_N_650_bdd_4_lut_9684.init = 16'h3f11;
    L6MUX21 i9126 (.D0(n17490), .D1(n17491), .SD(cnt_write[3]), .Z(oled_dat_N_672));
    LUT4 i1_4_lut_adj_150 (.A(state_back[4]), .B(n27), .C(n18381), .D(n8_adj_2), 
         .Z(state_back_5__N_285[4])) /* synthesis lut_function=(A (B+!(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[13:18])
    defparam i1_4_lut_adj_150.init = 16'h8a88;
    LUT4 n18001_bdd_4_lut_4_lut (.A(cnt_scan[2]), .B(char_reg[1]), .C(n4181), 
         .D(n18427), .Z(n18290)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam n18001_bdd_4_lut_4_lut.init = 16'hd5c0;
    LUT4 i1_2_lut_2_lut (.A(cnt_scan[2]), .B(n18036), .Z(n61_adj_8)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_2_lut_2_lut.init = 16'h4444;
    LUT4 i1_2_lut_adj_151 (.A(cnt_scan[3]), .B(n11418), .Z(n9_adj_4)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(135[8:13])
    defparam i1_2_lut_adj_151.init = 16'hdddd;
    LUT4 n3446_bdd_2_lut_9565_2_lut (.A(cnt_scan[2]), .B(n18125), .Z(n18126)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam n3446_bdd_2_lut_9565_2_lut.init = 16'h4444;
    LUT4 n7097_bdd_3_lut_9309 (.A(temp_l_c_2), .B(cnt_main[0]), .C(cnt_main[2]), 
         .Z(n17765)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam n7097_bdd_3_lut_9309.init = 16'h2020;
    LUT4 n3446_bdd_2_lut_9517_2_lut (.A(cnt_scan[2]), .B(n18111), .Z(n18112)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam n3446_bdd_2_lut_9517_2_lut.init = 16'h4444;
    LUT4 i9279_4_lut (.A(n17208), .B(n18389), .C(n18415), .D(state[0]), 
         .Z(clk_c_enable_73)) /* synthesis lut_function=(A+!(B+!(C (D)))) */ ;
    defparam i9279_4_lut.init = 16'hbaaa;
    LUT4 i4_4_lut (.A(n18379), .B(n17207), .C(n14000), .D(cnt_init[2]), 
         .Z(n17208)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i4_4_lut.init = 16'h0400;
    LUT4 i1_3_lut_adj_152 (.A(cnt_init[1]), .B(state[0]), .C(state[2]), 
         .Z(n17207)) /* synthesis lut_function=(!(A+(B (C)+!B !(C)))) */ ;
    defparam i1_3_lut_adj_152.init = 16'h1414;
    LUT4 i1_4_lut_adj_153 (.A(cnt_scan[4]), .B(cnt_scan[2]), .C(cnt_scan[3]), 
         .D(n18398), .Z(n4181)) /* synthesis lut_function=(A+(B (C)+!B !(C+!(D)))) */ ;
    defparam i1_4_lut_adj_153.init = 16'hebea;
    LUT4 i5674_2_lut (.A(n288), .B(oled_dcn_N_650), .Z(n314)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5674_2_lut.init = 16'h2222;
    PFUMX i47_adj_154 (.BLUT(n6_adj_68), .ALUT(n12_adj_69), .C0(state[3]), 
          .Z(n24_adj_67));
    LUT4 i1_4_lut_4_lut_adj_155 (.A(cnt_scan[2]), .B(cnt_scan[1]), .C(n17255), 
         .D(n10248), .Z(n61)) /* synthesis lut_function=(!(A+!(B (C)+!B (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i1_4_lut_4_lut_adj_155.init = 16'h5140;
    LUT4 n3446_bdd_2_lut_9504 (.A(n18071), .B(state[2]), .Z(n18072)) /* synthesis lut_function=(A (B)) */ ;
    defparam n3446_bdd_2_lut_9504.init = 16'h8888;
    LUT4 i5671_2_lut (.A(n287), .B(oled_dcn_N_650), .Z(n313)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[19:29])
    defparam i5671_2_lut.init = 16'h2222;
    PFUMX i47_adj_156 (.BLUT(n6_adj_46), .ALUT(n12), .C0(state[3]), .Z(n24_adj_45));
    LUT4 i1_4_lut_adj_157 (.A(n24), .B(state_back[3]), .C(n18381), .D(n27), 
         .Z(state_back_5__N_285[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_157.init = 16'hce0a;
    LUT4 i92_4_lut_4_lut (.A(cnt_scan[2]), .B(n17458), .C(cnt_scan[3]), 
         .D(n15863), .Z(n57_adj_15)) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam i92_4_lut_4_lut.init = 16'h4f40;
    LUT4 mux_65_i4_4_lut (.A(n445), .B(n456), .C(n9_adj_4), .D(n18375), 
         .Z(cnt_scan_4__N_308[3])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(120[16] 121[40])
    defparam mux_65_i4_4_lut.init = 16'hc505;
    LUT4 n3446_bdd_2_lut_9435_2_lut (.A(cnt_scan[2]), .B(n18005), .Z(n18006)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(62[4] 171[11])
    defparam n3446_bdd_2_lut_9435_2_lut.init = 16'h4444;
    LUT4 i1786_2_lut_rep_239 (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n18412)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(142[25:41])
    defparam i1786_2_lut_rep_239.init = 16'h8888;
    LUT4 i3_4_lut_adj_158 (.A(num[6]), .B(num[5]), .C(n18378), .D(num[7]), 
         .Z(n445)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[11:14])
    defparam i3_4_lut_adj_158.init = 16'hfffe;
    PFUMX i47_adj_159 (.BLUT(n6_adj_55), .ALUT(n12_adj_56), .C0(state[3]), 
          .Z(n24_adj_54));
    LUT4 i9254_3_lut (.A(num[2]), .B(num[1]), .C(num[0]), .Z(n11097)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i9254_3_lut.init = 16'h0101;
    LUT4 i1_4_lut_adj_160 (.A(n24_adj_32), .B(state_back[2]), .C(n18381), 
         .D(n27), .Z(state_back_5__N_285[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_160.init = 16'hce0a;
    LUT4 i1791_2_lut_3_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[2]), 
         .Z(n2386)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(142[25:41])
    defparam i1791_2_lut_3_lut.init = 16'h7878;
    PFUMX i91_adj_161 (.BLUT(n57), .ALUT(n61), .C0(cnt_scan[3]), .Z(n63));
    LUT4 mux_65_i3_4_lut (.A(n445), .B(n457), .C(n9_adj_4), .D(n18375), 
         .Z(cnt_scan_4__N_308[2])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(120[16] 121[40])
    defparam mux_65_i3_4_lut.init = 16'hc505;
    PFUMX i47_adj_162 (.BLUT(n6_adj_48), .ALUT(n12_adj_49), .C0(state[3]), 
          .Z(n24_adj_47));
    LUT4 i1798_2_lut_3_lut_4_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[3]), 
         .D(cnt_write[2]), .Z(n2385)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(142[25:41])
    defparam i1798_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i5676_2_lut (.A(n2131), .B(num[4]), .Z(n647)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[59:71])
    defparam i5676_2_lut.init = 16'h2222;
    LUT4 i2_4_lut_adj_163 (.A(n11483), .B(state[2]), .C(n35), .D(n31), 
         .Z(state_back_5__N_285[1])) /* synthesis lut_function=(A+(B (C)+!B (C+(D)))) */ ;
    defparam i2_4_lut_adj_163.init = 16'hfbfa;
    LUT4 i1_4_lut_adj_164 (.A(state[0]), .B(n14000), .C(state[2]), .D(state_back_5__N_620[1]), 
         .Z(n11483)) /* synthesis lut_function=(!(A (B+(C))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_164.init = 16'h1202;
    LUT4 i1_4_lut_adj_165 (.A(state_back[1]), .B(n18399), .C(n24_adj_31), 
         .D(n18411), .Z(n35)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i1_4_lut_adj_165.init = 16'haaa8;
    PFUMX i9124 (.BLUT(n17486), .ALUT(n17487), .C0(cnt_write[2]), .Z(n17490));
    PFUMX i47_adj_166 (.BLUT(n6_adj_51), .ALUT(n12_adj_52), .C0(state[3]), 
          .Z(n24_adj_50));
    PFUMX i47_adj_167 (.BLUT(n6_adj_62), .ALUT(n12_adj_63), .C0(state[3]), 
          .Z(n24_adj_61));
    LUT4 n18_bdd_4_lut_4_lut (.A(state[0]), .B(cnt_init[0]), .C(cnt_init[1]), 
         .D(cnt_init[2]), .Z(n17872)) /* synthesis lut_function=(!(A (B (C (D))+!B (C+!(D)))+!A (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(61[12] 172[6])
    defparam n18_bdd_4_lut_4_lut.init = 16'h0fdd;
    PFUMX i47_adj_168 (.BLUT(n6_adj_65), .ALUT(n12_adj_66), .C0(state[3]), 
          .Z(n24_adj_64));
    PFUMX i47_adj_169 (.BLUT(n6_adj_33), .ALUT(n17218), .C0(state[3]), 
          .Z(n24_adj_32));
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

